On Sun, Nov 28, 2010 at 01:19:18AM +0100, Idwer Vollering wrote: > Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM > registers on ICH5. > Add ICH5 and i865 to the supported chips list. > Enable the dumping of BAR6 on i865. > > Signed-off-by: Idwer Vollering <vid...@gmail.com>
Thanks, r6197 with some small modifications and cosmetic fixes. > Index: cpu.c > =================================================================== > --- cpu.c (revision 6128) > +++ cpu.c (working copy) [...] > + static const msr_entry_t modelf2x_global_msrs[] = { > + { 0x0000, "IA32_P5_MC_ADDR" }, > + { 0x0001, "IA32_P5_MC_TYPE" }, I removed a few of the MSRs that are marked as non-available for model 2, and added comments mentioning such MSRs. > + case PCI_DEVICE_ID_INTEL_ICH5: > + gpiobase = pci_read_word(sb, 0x58) & 0xfffc; The 0xfffc here and in other places is not correct I think, will post a fixup patch for this later. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot