Hi all,
Acked-by: Marc Bertens <mbertens.xs4all.nl>
Tested-by: Marc Bertens <mbertens.xs4all.nl>
Here is a new patch for the Nokia IP530, it contains;
* Selection of the P3 cup in the Kconfig
* In Kconfig the board revision can be selected.
* In the devicetree,cb added comments and commented-out some things that
where not needed, but for now left them in the file.
* New PIRQ table for board revision B, did this by some macros to keep
it simple.
Marc Bertens
Index: src/mainboard/nokia/ip530/Kconfig
===================================================================
--- src/mainboard/nokia/ip530/Kconfig (revision 6257)
+++ src/mainboard/nokia/ip530/Kconfig (working copy)
@@ -22,6 +22,7 @@
def_bool y
select ARCH_X86
select CPU_INTEL_SOCKET_PGA370
+ select CPU_INTEL_MODEL_68X
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_SMSC_SMSCSUPERIO
@@ -70,4 +74,31 @@
hex
default 0x00007522
+choice
+ prompt "Mainboard model"
+ depends on BOARD_NOKIA_IP530
+
+config BOARD_NOKIA_IP530_REV_A
+ bool "Revision A"
+ help
+ This determine the board revision and from that the PIRQ table
+
+config BOARD_NOKIA_IP530_REV_B
+ bool "Revision B (through E ?)"
+ help
+ This determine the board revision and from that the PIRQ table
+
+endchoice
+if BOARD_NOKIA_IP530_REV_A
+ config BOARD_NOKIA_IP530_REV
+ int
+ default 1
+endif
+if BOARD_NOKIA_IP530_REV_B
+ config BOARD_NOKIA_IP530_REV
+ int
+ default 2
+endif
+
+
endif # BOARD_NOKIA_IP530
Index: src/mainboard/nokia/ip530/devicetree.cb
===================================================================
--- src/mainboard/nokia/ip530/devicetree.cb (revision 6257)
+++ src/mainboard/nokia/ip530/devicetree.cb (working copy)
@@ -51,13 +51,14 @@
irq 0xB2 = 0x0C # Soft power status 1
irq 0xB3 = 0x05 # Soft power status 2
irq 0xC0 = 0x03 # IRQ MUX control
-
+ # setting up the PINs to there function, ie. GPIO, IRQ or other function
irq 0xC8 = 0x10 # GP50 = (I/O) output = Flashrom enable
irq 0xCA = 0x09 # GP52 = IRQ8 (output)
irq 0xCB = 0x01 # GP53 = nROMCS (output)
irq 0xCC = 0x11 # GP54 = (I/O) input
- irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
-
+## This line can go !!!!
+# irq 0xF9 = 0x00 # read/write GP5x lines (0x1C)
+ # setting up the PINs to there function, ie. GPIO, IRQ or other function
irq 0xD0 = 0x08 # GP60 = IRQ1
irq 0xD1 = 0x08 # GP61 = IRQ3
irq 0xD2 = 0x08 # GP62 = IRQ4
@@ -66,17 +67,19 @@
irq 0xD5 = 0x11 # GP65 = (I/O) input
irq 0xD6 = 0x08 # GP66 = IRQ8
irq 0xD7 = 0x11 # GP67 = (I/O) input
- irq 0xFA = 0x00 # read/write GP6x lines (0x88)
-
- irq 0xE0 = 0x00 # GP10 (I/O) = output
- irq 0xE1 = 0x01 # GP11 (I/O) = input
+## This line can go !!!!
+# irq 0xFA = 0x00 # read/write GP6x lines (0x88)
+ # setting up the PINs to there function, ie. GPIO, IRQ or other function
+ irq 0xE0 = 0x00 # GP10 (I/O) = output to DI of 93LC46 (1024 bits of EEPROM)
+ irq 0xE1 = 0x01 # GP11 (I/O) = input from DO of 93LC46
+ irq 0xE4 = 0x00 # GP14 (I/O) = output to SK of 93LC46
+ irq 0xE5 = 0x00 # GP15 (I/O) = output to CS of 93LC46
irq 0xE2 = 0x08 # GP12 = P17
irq 0xE3 = 0x00 # GP13 (I/O) = output = LED fault on front, active low
- irq 0xE4 = 0x00 # GP14 (I/O) = output
- irq 0xE5 = 0x00 # GP15 (I/O) = output
irq 0xE6 = 0x01 # GP16 (I/O) = input = JP900 on board, low on short, high on open
irq 0xE7 = 0x00 # GP17 (I/O) = output = LED alert on front, active low
- irq 0xF6 = 0xFF # read/write GP1x lines (0xCA)
+ # Make sure that the LEDs are off and set all EEPROM lines HIGH
+ irq 0xF6 = 0xAC # read/write GP1x lines (0xCA)
irq 0xEF = 0x00 # GP_INT2 disable
irq 0xF0 = 0x00 # GP_INT1 disable
Index: src/mainboard/nokia/ip530/irq_tables.c
===================================================================
--- src/mainboard/nokia/ip530/irq_tables.c (revision 6257)
+++ src/mainboard/nokia/ip530/irq_tables.c (working copy)
@@ -19,9 +19,21 @@
*/
#include <arch/pirq_routing.h>
+/*
+ * This IRQ mask enables the following lines 5, 6, 10, 11
+ * IRQ-lines FEDCBA9876543210
+ * 0x1E20 = 0001111000100000
+ * 0x0C60 = 0000110001100000 (current)
+ */
+#define PIRQ_IRQ_MASK 0x0C60
+/*
+ * The define PIRQ_ENTRY is just to keep it simple in the table below
+ */
+#define PIRQ_ENTRY( domain, device, lnka, lnkb, lnkc, lnkd, irqmask, slot ) \
+ { domain, (device << 3) | 0x0, {{lnka, irqmask}, {lnkb, irqmask}, {lnkc, irqmask}, {lnkd, irqmask}}, slot, 0x0 }
-#define PIRQ_IRQ_MASK 0x0c60
+
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
@@ -33,51 +45,55 @@
0x122e, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0xD7, /* Checksum */
- {
+#if CONFIG_BOARD_NOKIA_IP530_REV == 1
+ 0x78 /* Checksum for board rev A */
+#elif CONFIG_BOARD_NOKIA_IP530_REV == 2
+ 0xD9 /* Checksum for board rev B */
+#endif
+ , {
/**
- * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
- * FEDCBA9876543210
- * 0x1E20 = 0001111000100000
- * 0x0C60 = 0000110001100000
+ * The PIRQ table for board revision A and B (works with rev E ?).
*/
- // Southbridge 82371EB, INTD = 0x63
- { 0x00, (0x07 << 3) | 0x0, {{0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ // Southbridge 82371, INTD = 0x63
+ PIRQ_ENTRY( 0x00, 0x07, 0x00, 0x00, 0x00, 0x63, PIRQ_IRQ_MASK, 0x00 ),
// On-board PCI-to-PCI bridge
- { 0x01, (0x00 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // ETH1 on front panel, INTA = 0x62 = ok
- { 0x00, (0x0d << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
-
- // ETH2 on front panel, 0x63
- { 0x00, (0x0e << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // ETH3 on front panel = 0x60
- { 0x02, (0x04 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
-
- // ETH4 on front panel, INTA = 0x61 = ok
- { 0x02, (0x05 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCMCIA/Cardbus controller, INTA = 0x60 = ok, INTB = 0x61 = ok
- { 0x00, (0x0f << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}, {0x00, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ PIRQ_ENTRY( 0x01, 0x00, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x00 ),
+ // ETH1 on front panel
+ PIRQ_ENTRY( 0x00, 0x0d, 0x62, 0x00, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+ // ETH2 on front panel
+ PIRQ_ENTRY( 0x00, 0x0e, 0x63, 0x00, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+ // ETH3 on front panel
+ PIRQ_ENTRY( 0x02, 0x04, 0x60, 0x00, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+ // ETH4 on front panel
+ PIRQ_ENTRY( 0x02, 0x05, 0x61, 0x00, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+#if CONFIG_BOARD_NOKIA_IP530_REV == 1
+ // PCMCIA/Cardbus controller
+ PIRQ_ENTRY( 0x00, 0x0f, 0x60, 0x61, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+#elif CONFIG_BOARD_NOKIA_IP530_REV == 2
+ // PCMCIA/Cardbus controller
+ PIRQ_ENTRY( 0x00, 0x0f, 0x60, 0x00, 0x00, 0x00, PIRQ_IRQ_MASK, 0x00 ),
+#endif
// Bridge for slot 1 (top)
- { 0x02, (0x07 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x64, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ PIRQ_ENTRY( 0x02, 0x07, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x00 ),
// PCI compact slots 1 (top)
- { 0x03, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x1, 0x0 },
- { 0x03, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x2, 0x0 },
- { 0x03, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x3, 0x0 },
- { 0x03, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x4, 0x0 },
+ PIRQ_ENTRY( 0x03, 0x04, 0x61, 0x62, 0x63, 0x60, PIRQ_IRQ_MASK, 0x01 ),
+ PIRQ_ENTRY( 0x03, 0x05, 0x62, 0x63, 0x60, 0x61, PIRQ_IRQ_MASK, 0x02 ),
+ PIRQ_ENTRY( 0x03, 0x06, 0x63, 0x60, 0x61, 0x62, PIRQ_IRQ_MASK, 0x03 ),
+ PIRQ_ENTRY( 0x03, 0x07, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x04 ),
// Bridge for slot 2 (middle)
- { 0x02, (0x06 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
- // PCI compact slots 2 (middle)
- { 0x04, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x5, 0x0 },
- { 0x04, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0x6, 0x0 },
- { 0x04, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0x7, 0x0 },
- { 0x04, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0x8, 0x0 },
+ PIRQ_ENTRY( 0x02, 0x06, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x00 ),
+ // PCI compact sl63ots 2 (middle)
+ PIRQ_ENTRY( 0x04, 0x04, 0x61, 0x62, 0x63, 0x60, PIRQ_IRQ_MASK, 0x05 ),
+ PIRQ_ENTRY( 0x04, 0x05, 0x62, 0x63, 0x60, 0x61, PIRQ_IRQ_MASK, 0x06 ),
+ PIRQ_ENTRY( 0x04, 0x06, 0x63, 0x60, 0x61, 0x62, PIRQ_IRQ_MASK, 0x07 ),
+ PIRQ_ENTRY( 0x04, 0x07, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x08 ),
// Bridge for slot 3 (bottom)
- { 0x00, (0x10 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x0, 0x0 },
+ PIRQ_ENTRY( 0x00, 0x10, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x00 ),
// PCI compact slots 3 (bottom)
- { 0x05, (0x04 << 3) | 0x0, {{0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}}, 0x9, 0x0 },
- { 0x05, (0x05 << 3) | 0x0, {{0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}}, 0xA, 0x0 },
- { 0x05, (0x06 << 3) | 0x0, {{0x63, PIRQ_IRQ_MASK}, {0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}}, 0xB, 0x0 },
- { 0x05, (0x07 << 3) | 0x0, {{0x60, PIRQ_IRQ_MASK}, {0x61, PIRQ_IRQ_MASK}, {0x62, PIRQ_IRQ_MASK}, {0x63, PIRQ_IRQ_MASK}}, 0xC, 0x0 },
+ PIRQ_ENTRY( 0x05, 0x04, 0x61, 0x62, 0x63, 0x60, PIRQ_IRQ_MASK, 0x09 ),
+ PIRQ_ENTRY( 0x05, 0x05, 0x62, 0x63, 0x60, 0x61, PIRQ_IRQ_MASK, 0x0A ),
+ PIRQ_ENTRY( 0x05, 0x06, 0x63, 0x60, 0x61, 0x62, PIRQ_IRQ_MASK, 0x0B ),
+ PIRQ_ENTRY( 0x05, 0x07, 0x60, 0x61, 0x62, 0x63, PIRQ_IRQ_MASK, 0x0C ),
}
};
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