Author: zbao
Date: Thu Jan 20 06:59:22 2011
New Revision: 6280
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6280
Log:
S3 feanture of SB800. Compiliant with SB700.
Signed-off-by: Zheng Bao <zheng....@amd.com>
Acked-by: Zheng Bao <zheng....@amd.com>
Modified:
trunk/src/southbridge/amd/sb800/early_setup.c
trunk/src/southbridge/amd/sb800/sb800.h
Modified: trunk/src/southbridge/amd/sb800/early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/sb800/early_setup.c Thu Jan 20 06:41:11
2011 (r6279)
+++ trunk/src/southbridge/amd/sb800/early_setup.c Thu Jan 20 06:59:22
2011 (r6280)
@@ -646,4 +646,54 @@
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
+
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
+ int i;
+ printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword,
size, nvram_pos);
+
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ nvram_pos++;
+ }
+
+ return nvram_pos;
+}
+
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
+ u32 data = *old_dword;
+ int i;
+ for (i = 0; i<size; i++) {
+ outb(nvram_pos, BIOSRAM_INDEX);
+ data &= ~(0xff << (i * 8));
+ data |= inb(BIOSRAM_DATA) << (i *8);
+ nvram_pos++;
+ }
+ *old_dword = data;
+ printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n",
*old_dword, size,
+ nvram_pos-size);
+ return nvram_pos;
+}
+
+#if CONFIG_HAVE_ACPI_RESUME == 1
+static int acpi_is_wakeup_early(void) {
+ u16 tmp;
+ tmp = inw(ACPI_PM1_CNT_BLK);
+ printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
+ return (((tmp & (7 << 10)) >> 10) == 3);
+}
+#endif
+
+struct cbmem_entry *get_cbmem_toc(void) {
+ uint32_t xdata = 0;
+ int xnvram_pos = 0xfc, xi;
+ for (xi = 0; xi<4; xi++) {
+ outb(xnvram_pos, BIOSRAM_INDEX);
+ xdata &= ~(0xff << (xi * 8));
+ xdata |= inb(BIOSRAM_DATA) << (xi *8);
+ xnvram_pos++;
+ }
+ return (struct cbmem_entry *) xdata;
+}
+
#endif
Modified: trunk/src/southbridge/amd/sb800/sb800.h
==============================================================================
--- trunk/src/southbridge/amd/sb800/sb800.h Thu Jan 20 06:41:11 2011
(r6279)
+++ trunk/src/southbridge/amd/sb800/sb800.h Thu Jan 20 06:59:22 2011
(r6280)
@@ -24,6 +24,8 @@
#include "chip.h"
/* Power management index/data registers */
+#define BIOSRAM_INDEX 0xcd4
+#define BIOSRAM_DATA 0xcd5
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
@@ -47,6 +49,8 @@
#define REV_SB800_A11 0x11
#define REV_SB800_A12 0x12
+void sb800_enable(device_t dev);
+
#ifdef __PRE_RAM__
void sb800_lpc_port80(void);
void sb800_pci_port80(void);
@@ -55,7 +59,9 @@
/* void sb800_setup_sata_phys(struct device *dev); */
#endif
-void sb800_enable(device_t dev);
+int s3_save_nvram_early(u32 dword, int size, int nvram_pos);
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+
void sb800_enable_usbdebug(unsigned int port);
#endif /* SB800_H */
--
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