Author: sduplichan
Date: Thu Feb 10 21:49:56 2011
New Revision: 6342
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6342
Log:
According to AMD documentation, cache type WP should be used for
execution from flash memory. Coreboot uses WB. While there is no
noticeable performance difference between the two settings, use
of WB can cause a problem for a jtag debugger. The attached
patch changes AMD cache as ram setting for flash execution from
WB to WP.
Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Marc Jones <marcj...@gmail.com>
Modified:
trunk/src/cpu/amd/car/cache_as_ram.inc
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Feb 10 09:49:57 2011
(r6341)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc Thu Feb 10 21:49:56 2011
(r6342)
@@ -294,11 +294,11 @@
xorl %edx, %edx
/*
* IMPORTANT: The two lines below can _not_ be written like this:
- * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+ * movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRPROT), %eax
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ orl $MTRR_TYPE_WRPROT, %eax
wrmsr
movl $MTRRphysMask_MSR(1), %ecx
--
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