Author: svens
Date: Tue May 3 09:55:43 2011
New Revision: 6554
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6554
Log:
Enable caching for ROM area in model_6ex/cache_as_ram.inc
Signed-off-by: Sven Schnelle <sv...@stackframe.org>
Acked-by: Sven Schnelle <sv...@stackframe.org>
Modified:
trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue May 3 09:55:30
2011 (r6553)
+++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue May 3 09:55:43
2011 (r6554)
@@ -201,7 +201,17 @@
xorl %edx, %edx
wrmsr
movl $MTRRphysMask_MSR(0), %ecx
- movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+ movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+ movl $0x0000000f, %edx // 36bit address space
+ wrmsr
+
+ /* Enable caching and Speculative Reads for the last 4MB. */
+ movl $MTRRphysBase_MSR(1), %ecx
+ movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+ xorl %edx, %edx
+ wrmsr
+ movl $MTRRphysMask_MSR(1), %ecx
+ movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
movl $0x0000000f, %edx // 36bit address space
wrmsr
--
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