Author: mjones Date: Sun May 15 23:26:04 2011 New Revision: 6578 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6578
Log: Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Marc Jones <marcj...@gmail.com> Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig trunk/src/vendorcode/amd/cimx/sb800/OEM.h Modified: trunk/src/mainboard/amd/persimmon/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/mainboard/amd/persimmon/dsdt.asl Sun May 15 23:26:04 2011 (r6578) @@ -36,7 +36,7 @@ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ Name(PBLN, 0x0) /* Length of BIOS area */ - Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(PCBA, 0xF8000000) /* Base address of PCIe config space */ Name(HPBA, 0xFED00000) /* Base address of HPET table */ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ Modified: trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig ============================================================================== --- trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/northbridge/amd/agesa_wrapper/family14/Kconfig Sun May 15 23:26:04 2011 (r6578) @@ -41,12 +41,12 @@ config MMCONF_BASE_ADDRESS hex - default 0xe0000000 + default 0xf8000000 depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 config MMCONF_BUS_NUMBER int - default 256 + default 16 depends on NORTHBRIDGE_AMD_AGESA_WRAPPER_FAMILY14 config DIMM_DDR3 Modified: trunk/src/vendorcode/amd/cimx/sb800/OEM.h ============================================================================== --- trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sun May 15 23:19:54 2011 (r6577) +++ trunk/src/vendorcode/amd/cimx/sb800/OEM.h Sun May 15 23:26:04 2011 (r6578) @@ -48,7 +48,7 @@ #ifdef MOVE_PCIEBAR_TO_F0000000 #define PCIEX_BASE_ADDRESS 0xF7000000 #else - #define PCIEX_BASE_ADDRESS 0xE0000000 + #define PCIEX_BASE_ADDRESS 0xF8000000 #endif /** -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot