Tadas,
On Mon, Aug 1, 2011 at 1:08 PM, Tadas Slotkus <devta...@gmail.com> wrote: > Hi, thank you both for the answers. I have studied libpci from > libpayload and removed that device list generation with mallocs. Done a > bunch of trial-error cleanup and now chipset enable and probing for > flash works in ramstage's top of hardwaremain function with this line > included: > x86_setup_mtrrs(36); //from cpu init routine > see attached log: ramstage_with_mtrr.txt. > Also attaching nonworking logs in romstage and ramstage. > > Now the question is how these mtrrs should be set in cache_as_ram.inc or > maybe I'm totally wrong? :) You will need the MTRR setup from CAR. You will want your code to execute in the XIP area, so that it may be cashed. You may still have stack/mem issues. That may be the first place you look for problems. You may need to find a way to optimize for resources. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
