* Alp Eren Köse <alperenk...@buyutech.com.tr> [111018 11:25]: > Hi thanks all for your help, > > I have arranged the "devicetree.cb" as suggested, you can see it at the > attachment. > Put the superio chip under the LPC bridge section, but I didn't get how did > you > know it? > > Added those to the romstage.c: > > #include "superio/winbond/w83627hf/early_serial.c" > > #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) > > w83627hf_set_clksel_48(SERIAL_DEV); > > main() looks like this now: > ....... // omitted > sch_enable_lpc(); > w83627hf_set_clksel_48(SERIAL_DEV); // NEWLY ADDED > w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); // NEWLY ADDED > uart_init(); // NEWLY ADDED ^^^^^^^^^^^^^^^^^ Not needed (in fact, it's wrong to put it there)
> By the way all I get is \0x00 when I open the board and another \0x00 when I > close it.. Do you have your CMC binary at the location it's strapped to by hardware? Do you get port 80 post codes? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot