Sven Schnelle (sv...@stackframe.org) just uploaded a new patch set to gerrit, 
which you can find at http://review.coreboot.org/331

-gerrit

commit eb04888eaf8417fe9cdb59718fd2d06cd5e98308
Author: Sven Schnelle <sv...@stackframe.org>
Date:   Sun Oct 23 16:57:50 2011 +0200

    X60: enable Cx power saving modes
    
    Change-Id: Ib03d9aa77050edde2538b80b32158cb3f0610be6
    Signed-off-by: Sven Schnelle <sv...@stackframe.org>
---
 src/mainboard/lenovo/x60/Kconfig       |    1 +
 src/mainboard/lenovo/x60/devicetree.cb |   18 ++++++++++++++++++
 src/mainboard/lenovo/x60/mainboard.c   |   13 +++++++++++++
 3 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
index c4b2f63..1784505 100644
--- a/src/mainboard/lenovo/x60/Kconfig
+++ b/src/mainboard/lenovo/x60/Kconfig
@@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select SUPERIO_NSC_PC87392
        select EC_LENOVO_PMH7
        select EC_LENOVO_H8
+       select DRIVERS_ICS_954309
        select BOARD_HAS_FADT
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/lenovo/x60/devicetree.cb 
b/src/mainboard/lenovo/x60/devicetree.cb
index 55e0b2d..000f9c7 100644
--- a/src/mainboard/lenovo/x60/devicetree.cb
+++ b/src/mainboard/lenovo/x60/devicetree.cb
@@ -60,6 +60,8 @@ chip northbridge/intel/i945
 
                        register "gpe0_en" = "0x11000006"
                        register "alt_gp_smi_en" = "0x1000"
+
+                       register "c4onc3_enable" = "1"
                        device pci 1b.0 on # Audio Cnotroller
                                subsystemid 0x17aa 0x2010
                        end
@@ -174,6 +176,22 @@ chip northbridge/intel/i945
                        end
                        device pci 1f.3 on # SMBUS
                                subsystemid 0x17aa 0x200f
+                               chip drivers/ics/954309
+                                       register "reg0" = "0x2e"
+                                       register "reg1" = "0xf7"
+                                       register "reg2" = "0x3c"
+                                       register "reg3" = "0x20"
+                                       register "reg4" = "0x01"
+                                       register "reg5" = "0x00"
+                                       register "reg6" = "0x1b"
+                                       register "reg7" = "0x01"
+                                       register "reg8" = "0x54"
+                                       register "reg9" = "0xff"
+                                       register "reg10" = "0xff"
+                                       register "reg11" = "0x07"
+                                       device i2c 69 on end
+                               end
+
                        end
                end
                chip southbridge/ricoh/rl5c476
diff --git a/src/mainboard/lenovo/x60/mainboard.c 
b/src/mainboard/lenovo/x60/mainboard.c
index bf3d8d3..ef7d21f 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -36,6 +36,19 @@
 #include <northbridge/intel/i945/i945.h>
 #include <pc80/mc146818rtc.h>
 #include "dock.h"
+#include <arch/x86/include/arch/acpigen.h>
+
+static struct cst_entry cst_entries[] = {
+       { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
+       { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
+       { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
+};
+
+int get_cst_entries(struct cst_entry **entries)
+{
+       *entries = cst_entries;
+       return ARRAY_SIZE(cst_entries);
+}
 
 static void mainboard_enable(device_t dev)
 {

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