Patrick Georgi ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/346
-gerrit commit de146c35db3a771e779726bda61224455c1433ac Author: Patrick Georgi <[email protected]> Date: Thu Oct 6 14:36:08 2011 +0200 siemens/sitemp_g1p1: Add more devices to PIR and MP table Linux 2.4 is happier that way Change-Id: I016609ae1e004ec856e8223893352dcdd061b291 Signed-off-by: Patrick Georgi <[email protected]> --- src/mainboard/siemens/sitemp_g1p1/irq_tables.c | 5 ++ src/mainboard/siemens/sitemp_g1p1/mptable.c | 55 ++++++++++++++++++++++++ 2 files changed, 60 insertions(+), 0 deletions(-) diff --git a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c index b2a9668..186057d 100644 --- a/src/mainboard/siemens/sitemp_g1p1/irq_tables.c +++ b/src/mainboard/siemens/sitemp_g1p1/irq_tables.c @@ -117,6 +117,11 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq_info++; slot_num++; + /* ide */ + write_pirq_info(pirq_info, bus_sb600[0], ((sbdn_sb600 + 0x14) << 3) | 1, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 1, 0); + pirq_info++; + slot_num++; + pirq->size = 32 + 16 * slot_num; for (i = 0; i < pirq->size; i++) diff --git a/src/mainboard/siemens/sitemp_g1p1/mptable.c b/src/mainboard/siemens/sitemp_g1p1/mptable.c index 0e18fb3..9e4a6db 100644 --- a/src/mainboard/siemens/sitemp_g1p1/mptable.c +++ b/src/mainboard/siemens/sitemp_g1p1/mptable.c @@ -60,6 +60,61 @@ static void *smp_write_config_table(void *v) } mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0); +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) + + /* usb */ + PCI_INT(0x0, 0x13, 0x0, 0x10); + PCI_INT(0x0, 0x13, 0x1, 0x11); + PCI_INT(0x0, 0x13, 0x2, 0x12); + PCI_INT(0x0, 0x13, 0x3, 0x13); + + /* sata */ + PCI_INT(0x0, 0x12, 0x1, 0x16); + + /* SMBus/ACPI */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + /* IDE */ + PCI_INT(0x0, 0x14, 0x1, 0x11); + /* HDA */ + PCI_INT(0x0, 0x14, 0x2, 0x12); + /* LPC */ + PCI_INT(0x0, 0x14, 0x3, 0x13); + + /* GFX ? */ + PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); + PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); + + /* PCIe slots */ + PCI_INT(0x2, 0x00, 0x00, 0x10); + PCI_INT(0x2, 0x00, 0x01, 0x11); + PCI_INT(0x2, 0x00, 0x02, 0x12); + PCI_INT(0x2, 0x00, 0x03, 0x13); + + /* PCIe slots */ + PCI_INT(0x3, 0x00, 0x00, 0x11); + PCI_INT(0x3, 0x00, 0x01, 0x12); + PCI_INT(0x3, 0x00, 0x02, 0x13); + PCI_INT(0x3, 0x00, 0x03, 0x10); + + /* PCIe slots */ + PCI_INT(0x4, 0x00, 0x00, 0x12); + PCI_INT(0x4, 0x00, 0x01, 0x13); + PCI_INT(0x4, 0x00, 0x02, 0x10); + PCI_INT(0x4, 0x00, 0x03, 0x11); + + /* PCIe slots */ + PCI_INT(0x5, 0x00, 0x00, 0x13); + PCI_INT(0x5, 0x00, 0x01, 0x10); + PCI_INT(0x5, 0x00, 0x02, 0x11); + PCI_INT(0x5, 0x00, 0x03, 0x12); + + /* onboard NIC ? */ + PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13); + PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10); + PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11); + PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12); + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
