On Fri, 2011-10-28 at 22:56 +0200, Patrick Georgi wrote: > Am Fr 28 Okt 2011 07:18:36 CEST schrieb Kyösti Mälkki: > > I have trouble making dual fallback/normal image. > > [detailed report] > > Any thoughts? > The change in http://review.coreboot.org/351 should fix it > Thank you for the report. >
Thanks! Now I have some sort of controlled tiny fallback/normal boot, and I went for the Cache-As-Ram with my AOpen and have new trouble: When updating existing flash image, if my new normal/romstage is built with ROMCC it is aligned to CONFIG_XIP_ROM_SIZE boundary (excluding some CBFS header) and I can boot with it. If my new normal/romstage is built with GCC for Cache-As-Ram, the same alignment does not apply and on boot it halts before any serial output. Everything I have should be the latest git, including the MTRR $copy_and_run patch. CONFIG_XIP_ROM_BASE seems obsolete? Could you take CONFIG_XIP_ROM_SIZE from romstage CBFS-header and round that up? This is now 64kB while my romstage takes <16kB. So this wastes precious space on flash device. KM -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
