Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/382
-gerrit commit 957934ed3e56437cadc5c99d80149b2c7d35c0b4 Author: Florian Zumbiehl <[email protected]> Date: Tue Nov 1 20:19:03 2011 +0100 support for setting the Memory DQ Drive Strength register in amdk8 raminit Change-Id: Ic68c10b75bd0217540fb1f55dded1f9d7f5e8aea Signed-off-by: Florian Zumbiehl <[email protected]> --- src/northbridge/amd/amdk8/Kconfig | 9 +++++++++ src/northbridge/amd/amdk8/pre_f.h | 6 ++++++ src/northbridge/amd/amdk8/raminit.c | 21 +++++++++++++++++++++ 3 files changed, 36 insertions(+), 0 deletions(-) diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 858041a..2b87b64 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -45,6 +45,15 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n +config K8_DQ_DRIVE_STRENGTH_0 + bool +config K8_DQ_DRIVE_STRENGTH_15 + bool +config K8_DQ_DRIVE_STRENGTH_30 + bool +config K8_DQ_DRIVE_STRENGTH_50 + bool + config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/amd/amdk8/bootblock.c" diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index dae2d97..0d5f6fa 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -157,6 +157,12 @@ #define DCH_RDPREAMBLE_BASE ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MIN ((2<<1)+0) /* 2.0 ns */ #define DCH_RDPREAMBLE_MAX ((9<<1)+1) /* 9.5 ns */ +#define DCH_DQ_DRV_STRENGTH_SHIFT 13 +#define DCH_DQ_DRV_STRENGTH_MASK 3 +#define DCH_DQ_DRV_STRENGTH_0 0 +#define DCH_DQ_DRV_STRENGTH_15 1 +#define DCH_DQ_DRV_STRENGTH_30 2 +#define DCH_DQ_DRV_STRENGTH_50 3 #define DCH_IDLE_LIMIT_SHIFT 16 #define DCH_IDLE_LIMIT_MASK 0x7 #define DCH_IDLE_LIMIT_0 0 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 11288da..d8dcab8 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2193,6 +2193,27 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) printk(BIOS_DEBUG, "No memory for this cpu\n"); return; } + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 || CONFIG_K8_DQ_DRIVE_STRENGTH_15 || CONFIG_K8_DQ_DRIVE_STRENGTH_30 || CONFIG_K8_DQ_DRIVE_STRENGTH_50 + if (!is_cpu_pre_e0()) { + uint32_t dch, strength; + +#if CONFIG_K8_DQ_DRIVE_STRENGTH_0 + strength = DCH_DQ_DRV_STRENGTH_0; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_15 + strength = DCH_DQ_DRV_STRENGTH_15; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_30 + strength = DCH_DQ_DRV_STRENGTH_30; +#elif CONFIG_K8_DQ_DRIVE_STRENGTH_50 + strength = DCH_DQ_DRV_STRENGTH_50; +#endif + dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); + dch &= ~(DCH_DQ_DRV_STRENGTH_MASK << DCH_DQ_DRV_STRENGTH_SHIFT); + dch |= strength << DCH_DQ_DRV_STRENGTH_SHIFT; + pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); + } +#endif + dimm_mask = spd_enable_2channels(ctrl, dimm_mask); if (dimm_mask < 0) goto hw_spd_err; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
