Florian Zumbiehl just uploaded a new patch set to gerrit, which you can find at
http://review.coreboot.org/481
-gerrit
commit 242cb03ce02bde431666e5e6ac7d0eb1375eeba0
Author: Florian Zumbiehl <fl...@florz.de>
Date: Sat Dec 10 19:39:49 2011 +0100
k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <fl...@florz.de>
---
src/mainboard/asus/k8v-x/Kconfig | 1 +
src/northbridge/amd/amdk8/Kconfig | 6 ++++++
src/northbridge/amd/amdk8/raminit.c | 4 ++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
index d297143..114c609 100644
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ b/src/mainboard/asus/k8v-x/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select BOARD_ROMSIZE_KB_512
select RAMINIT_SYSINFO
select SET_FIDVID
+ select K8_FORCE_2T_DRAM_TIMING
config MAINBOARD_DIR
string
diff --git a/src/northbridge/amd/amdk8/Kconfig
b/src/northbridge/amd/amdk8/Kconfig
index 858041a..70e75e9 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -37,6 +37,12 @@ config MEM_TRAIN_SEQ
int
default 0
+# Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and
+# single DIMM is indeed unreliable without it).
+config K8_FORCE_2T_DRAM_TIMING
+ bool
+ default n
+
config HW_MEM_HOLE_SIZEK
hex
default 0x100000
diff --git a/src/northbridge/amd/amdk8/raminit.c
b/src/northbridge/amd/amdk8/raminit.c
index 98044d4..eb33a39 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1477,7 +1477,7 @@ hw_error:
if (dloading != 0) {
/* we have valid combination check the restrictions */
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
- dcl |= (dimm_loading_config[dpos][rpos] & DDR_2T) ? (DCL_En2T)
: 0;
+ dcl |= ((dimm_loading_config[dpos][rpos] & DDR_2T) ||
CONFIG_K8_FORCE_2T_DRAM_TIMING) ? (DCL_En2T) : 0;
/* Set DuallDimm is second channel is completely empty (revD+)
*/
if (((cpuid_eax(1) & 0xfff0f) >= 0x10f00) && ((dpos & 0x5) ==
0)) {
printk(BIOS_DEBUG, "Setting DualDIMMen\n");
@@ -1661,7 +1661,7 @@ static struct spd_set_memclk_result spd_set_memclk(const
struct mem_controller *
goto hw_error;
#if CONFIG_CPU_AMD_SOCKET_754
- if (freq < max_freq_1t) {
+ if (freq < max_freq_1t || CONFIG_K8_FORCE_2T_DRAM_TIMING) {
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW,
pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW) |
DCL_En2T);
}
--
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