On 12/29/11 4:30 AM, Benjamin Henrion wrote: > On Thu, Dec 29, 2011 at 3:22 AM, Philip Prindeville > <philipp_s...@redfish-solutions.com> wrote: >> Ok, I build coreboot's trunk and selected the target Alix2D, but managed to >> brick the device: >> >> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting... >> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e >> Configuring PLL. >> >> >> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 starting... >> MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e >> PLL configured. >> Castle 2.0 BTM periodic sync period. >> Enable Quack for fewer re-RAS on the MC >> GLIU port active enable >> Set the Delay Control in GLCP >> spd_read_byte dev 50 addr 0d returns 08 >> spd_read_byte dev 50 addr 05 returns 01 >> spd_read_byte dev 51 returns 0xff >> Enable RSDC >> FPU imprecise exceptions bit >> Enable Suspend on HLT & PAUSE instructions >> Enable SUSP and allow TSC to run in Suspend >> Setup throttling delays to proper mode >> Done cpuRegInit >> Ram1.00 >> Ram2.00 >> * sdram_set_spd_register >> spd_read_byte dev 50 addr 15 returns ff >> * Check DIMM 0 >> * Check DIMM 1 >> spd_read_byte dev 51 returns 0xff >> * Check DDR MAX >> spd_read_byte dev 50 addr 09 returns 0a >> spd_read_byte dev 51 returns 0xff >> * AUTOSIZE DIMM 0 >> * Check present >> spd_read_byte dev 50 addr 02 returns 07 >> * MODBANKS >> spd_read_byte dev 50 addr 05 returns 01 >> * FIELDBANKS >> spd_read_byte dev 50 addr 11 returns 04 >> * SPDNUMROWS >> spd_read_byte dev 50 addr 03 returns 03 >> spd_read_byte dev 50 addr 04 returns 0a >> * SPDBANKDENSITY >> spd_read_byte dev 50 addr 1f returns 40 >> * DIMMSIZE >> * BEFORT CTZ >> * TEST DIMM SIZE>8 >> * PAGESIZE >> spd_read_byte dev 50 addr 04 returns 0a >> * MAXCOLADDR >> * >12address test >> * RDMSR CF07 >> * WRMSR CF07 >> * ALL DONE >> * AUTOSIZE DIMM 1 >> * Check present >> spd_read_byte dev 51 returns 0xff >> * set cas latency >> spd_read_byte dev 50 addr 12 returns 10 >> spd_read_byte dev 50 addr 17 returns 3c >> spd_read_byte dev 50 addr 19 returns 4b >> spd_read_byte dev 51 returns 0xff >> * set all latency >> spd_read_byte dev 50 addr 1e returns 28 >> spd_read_byte dev 51 returns 0xff >> spd_read_byte dev 50 addr 1b returns 0f >> spd_read_byte dev 51 returns 0xff >> spd_read_byte dev 50 addr 1d returns 0f >> spd_read_byte dev 51 returns 0xff >> spd_read_byte dev 50 addr 1c returns 0a >> spd_read_byte dev 51 returns 0xff >> spd_read_byte dev 50 addr 2a returns 46 >> spd_read_byte dev 51 returns 0xff >> * set emrs >> spd_read_byte dev 50 addr 16 returns ff >> spd_read_byte dev 51 returns 0xff >> * set ref rate >> spd_read_byte dev 50 addr 0c returns 3a >> spd_read_byte dev 51 returns 0xff >> Ram3 >> * DRAM controller init done. >> >> RAM DLL lock >> Ram4 >> POST 02 >> Past wbinvd >> Loading image. >> Searching for fallback/coreboot_ram >> Check fallback/romstage >> Check fallback/coreboot_ram >> Stage: loading fallback/coreboot_ram @ 0x100000 (147456 bytes), entry @ >> 0x100000 >> Stage: done loading. >> Jumping to image. >> coreboot-4.0-1933-gded9388-dirty Wed Dec 28 16:14:58 MST 2011 booting... >> clocks_per_usec: 499 >> Enumerating buses... >> Show all devs...Before device enumeration. >> Root Device: enabled 1 >> PCI_DOMAIN: 0000: enabled 1 >> PCI: 00:01.0: enabled 1 >> PCI: 00:01.1: enabled 1 >> PCI: 00:0f.0: enabled 1 >> PCI: 00:0f.1: enabled 1 >> PCI: 00:0f.2: enabled 1 >> PCI: 00:0f.4: enabled 1 >> PCI: 00:0f.5: enabled 1 >> APIC_CLUSTER: 0: enabled 1 >> APIC: 00: enabled 1 >> Compare with tree... >> Root Device: enabled 1 >> PCI_DOMAIN: 0000: enabled 1 >> PCI: 00:01.0: enabled 1 >> PCI: 00:01.1: enabled 1 >> PCI: 00:0f.0: enabled 1 >> PCI: 00:0f.1: enabled 1 >> PCI: 00:0f.2: enabled 1 >> PCI: 00:0f.4: enabled 1 >> PCI: 00:0f.5: enabled 1 >> APIC_CLUSTER: 0: enabled 1 >> APIC: 00: enabled 1 >> scan_static_bus for Root Device >>>> Entering northbridge.c: enable_dev with path 6 >>>> Entering northbridge.c: pci_domain_enable >> Enter northbridge_init_early >> writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80 >> writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0 >> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 >> sizeram: sizem 0x100MB >> SysmemInit: enable for 256MBytes >> usable RAM: 268304383 bytes >> SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100 >> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 >> sizeram: sizem 0x100MB >> SMMGL0Init: 268304384 bytes >> SMMGL0Init: offset is 0x80400000 >> SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0 >> writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003 >> writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80 >> writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0 >> sizeram: _MSR MC_CF07_DATA: 10076013:00061a40 >> sizeram: sizem 0x100MB >> SysmemInit: enable for 256MBytes >> usable RAM: 268304383 bytes >> SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100 >> SMMGL1Init: >> SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0 >> writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001 >> writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0 >> CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00 >> CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000 >> L2 cache enabled >> Enabling cache >> GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000 >> GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000 >> Exit northbridge_init_early >> Done cpubug fixes >> Not Doing ChipsetFlashSetup() >> Preparing for VSA... >> VSA: Real mode stub @00000600: 862 bytes >> Searching for vsa >> Check fallback/romstage >> Check fallback/coreboot_ram >> Check fallback/payload >> Check config >> Check >> ERROR: No file header found at fffffd40, attempting to recover by searching >> for header >> Could not find file 'vsa'. >> Failed to load VSA. >> Graphics init... >> VRC_VG value: 0xffff >> Finding PCI configuration type. >> PCI: Sanity check failed >> pci_check_direct failed >> >> >> >> [hang] >> >> What am I missing? There doesn't seem to be a default VSA payload for the >> out-of-the-box default SeaBIOS build, which seems curious... >> >> I burned BIOS by doing the following: >> >> * boot the box up in linux >> * scp'd the coreboot.rom file over from my build box >> * flashrom -w coreboot.rom >> >> Those were hopefully the correct steps. > > You need to add the seabios thing in the .rom file. > > It seems you have hit the same problem as I had: > > http://www.zoobab.com/alix-1c#toc4 > > I have the plan to recover it with an LPC+arduinomega that I bought > recently, but have to find the time.
What's the difference between that VSA file and the amd_vsa_lx.bin that's in: svn://coreboot.org/vsa/trunk/gplvsa2 -Philip -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot