Kerry Sheh ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/568
-gerrit commit 40d0b33ba8a18805605c7818d45b48ed92d3c439 Author: Kerry Sheh <[email protected]> Date: Fri Jan 20 18:50:15 2012 +0800 H8QGI: supermicro/h8qgi xip size increase from 512K to 1M Bytes. Change-Id: I1fb1aaad68aed8b41253a02cc0bc151c239b0dbe Signed-off-by: Kerry Sheh <[email protected]> Signed-off-by: Kerry Sheh <[email protected]> --- src/mainboard/supermicro/h8qgi/Kconfig | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/src/mainboard/supermicro/h8qgi/Kconfig b/src/mainboard/supermicro/h8qgi/Kconfig index e900ea8..201df45 100644 --- a/src/mainboard/supermicro/h8qgi/Kconfig +++ b/src/mainboard/supermicro/h8qgi/Kconfig @@ -123,5 +123,19 @@ config VGA_BIOS_ID depends on VGA_BIOS default "102b,0532" +config XIP_ROM_BASE + hex + default 0xfff00000 + +config XIP_ROM_SIZE + hex + default 0x100000 + help + Overwride the default write through caching size as 1M Bytes. + On some AMD paltform, one socket support 2 kinds of processor family, + Compiling 2 cpu families agesa code will increase the romstage size. + In order to execute romstage in place on the flash rom, + more space is required to be set as write through caching. + endif # BOARD_SUPERMICRO_H8QGI -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
