Kyösti Mälkki ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/637
-gerrit commit e8a4832907c4ff5d126c32acde22a00ad35b6395 Author: Kyösti Mälkki <[email protected]> Date: Wed Feb 15 15:55:03 2012 +0200 Intel model_106cx: Use symbolic names for MTRR bits Change-Id: I6ea5ca631c22fe870224a498b68d77d85798b3f4 Signed-off-by: Kyösti Mälkki <[email protected]> --- src/cpu/intel/model_106cx/cache_as_ram.inc | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index eb3d650..824e341 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -63,14 +63,14 @@ clear_mtrrs: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax xorl %edx, %edx wrmsr /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr /* Enable L2 cache. */ @@ -113,7 +113,7 @@ clear_mtrrs: movl $MTRRphysMask_MSR(1), %ecx xorl %edx, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -155,7 +155,7 @@ clear_mtrrs: /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - andl $(~(1 << 11)), %eax + andl $(~MTRRdefTypeEn), %eax wrmsr post_code(0x31) @@ -196,7 +196,7 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | (1 << 11)), %eax + movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax xorl %edx, %edx wrmsr @@ -212,7 +212,7 @@ clear_mtrrs: /* Enable MTRR. */ movl $MTRRdefType_MSR, %ecx rdmsr - orl $(1 << 11), %eax + orl $MTRRdefTypeEn, %eax wrmsr post_code(0x3b) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
