So I have been working with hyper-threaded P4 NetBurst CPUs. Currently I have a dual-socket 604 with model f25 P4 Xeon CPUs that boots with the CAR code I have made available in git [1].
I have received a report of a non-HT f27 booting with my code [1] on a different mainboard and socket 478. On that mainboard, hyper-threaded non-Xeon P4 CPU models f29 and f49 fail before console. Using POST codes, we have traced the issue this far: 1. BSP CPU has successfully sent Start-Up IPI to AP CPU. 2. AP CPU has successfully received Start-Up IPI and has entered ap_sipi_vector and executes code from src/cpu/x86/16bit/entry16.inc At the time AP CPU executes "lidt", it seems both BSP and AP CPUs halt. a) Any reference to this null-limit method in Intel literature? b) Both limit of 0 and base of 0x00 for IDT seem incorrect to me. That would mean IDT is one byte at non-existing RAM adress 0x00. c) There is a longish explanation of LGDT parameter calculation. Why is this not applied to LIDT? Thanks, KM [1] http://review.coreboot.org/607 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
