Marc Jones ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670
-gerrit commit 15e268ee435d7d6f8d76997336efb38c4732042e Author: Marc Jones <[email protected]> Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <[email protected]> --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); - print_t(" ECCInit 2 \n"); - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ /* Reset MC4_STS. */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*Node has Dram */ } /*if Node present */ } - print_t(" ECCInit 3 \n"); if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..d126a95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6107e80 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node); + printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status); + printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus); + printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode); + printk(BIOS_DEBUG, "ECCInit: Done\n"); + } + } return MemClrECC; } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
