the following patch was just integrated into master:
commit a8aad29c8d4cd14fcc141f51bdc490771c9841fb
Author: Kyösti Mälkki <[email protected]>
Date: Thu Jun 28 21:50:43 2012 +0300
Intel model_106cx: change CAR to model_6ex
Diff between model_106cx and model_6ex CAR codes suggests currently
used model_106cx CAR is not optimal - destination RAM and source ROM
of ramstage copy_and_run are only partly set cacheable.
It appears variable MTRR setting for XIP cache is left enabled on
model_106cx code, where it should have extended to cover all of Flash.
Introduces untested functional change on boards:
intel/d945gclf
iwave/iWRainbowG6
Deletes file:
model_106cx/cache_as_ram.inc
Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d
Signed-off-by: Kyösti Mälkki <[email protected]>
Build-Tested: build bot (Jenkins) at Wed Jul 4 12:21:14 2012, giving +1
Reviewed-By: Sven Schnelle <[email protected]> at Wed Jul 4 14:45:38 2012,
giving +2
See http://review.coreboot.org/642 for details.
-gerrit
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