David Hendricks ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2041
-gerrit commit eb45ccbeba711e7be5146f080ffa304f12d5012f Author: David Hendricks <[email protected]> Date: Mon Dec 17 20:41:32 2012 -0800 Simplify romstage.ld for armv7 This is still a work-in-progress, but it seems to work better than before and is less complicated... Change-Id: I6f730d017391f9ec4401cdfd34931c869df10a9e Signed-off-by: Ronald G. Minnich <[email protected]> Signed-off-by: David Hendricks <[email protected]> --- src/arch/armv7/romstage.ld | 62 +++++++++------------------------------------- 1 file changed, 12 insertions(+), 50 deletions(-) diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld index 0a2f7f2..d2b69d7 100644 --- a/src/arch/armv7/romstage.ld +++ b/src/arch/armv7/romstage.ld @@ -29,7 +29,7 @@ * FIXME 2: Somehow linker didn't like CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE... */ /* MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x3800 } */ -MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 } +/*MEMORY { .sram : ORIGIN = 0x02023400, LENGTH = 0x10000 }*/ /* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") @@ -39,58 +39,20 @@ ENTRY(_start) SECTIONS { - . = ROMSTAGE_BASE; + /* FIXME: replace this with CPU-specific Kconfig variable */ + . = 0x02023400; /* Exynos5 */ - /* - .rom . : { + .romtext . : { _rom = .; - *(.rom.text); - *(.rom.data); + *(.text); + } + + .romdata . : { *(.rodata); - *(.rodata.*); - *(.rom.data.*); - . = ALIGN(16); + *(.machine_param); + . = ALIGN(8); _erom = .; } - */ - - /* First we place the code and read only data (typically const declared). - * This could theoretically be placed in rom. - */ - .text : { - _text = .; - *(.text); - *(.text.*); - . = ALIGN(4); - _etext = .; - } >.sram - - .rodata : { - _rodata = .; - . = ALIGN(4); - cpu_drivers = . ; - *(.rodata.cpu_driver) - ecpu_drivers = . ; - *(.rodata) - *(.rodata.*) - /* kevinh/Ispiri - Added an align, because the objcopy tool - * incorrectly converts sections that are not long word aligned. - */ - . = ALIGN(4); - - _erodata = .; - } >.sram - /* After the code we place initialized data (typically initialized - * global variables). This gets copied into ram by startup code. - * __data_start and __data_end shows where in ram this should be placed, - * whereas __data_loadstart and __data_loadend shows where in rom to - * copy from. - */ - .data : { - _data = .; - *(.data) - _edata = .; - } >.sram __image_copy_end = .; @@ -99,12 +61,12 @@ SECTIONS * crt0.S fills between _bss and _ebss with zeroes. */ .bss . : { - . = ALIGN(4); + . = ALIGN(8); _bss = .; *(.bss) *(.sbss) *(COMMON) - } >.sram + } _ebss = .; _end = .; -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
