Jens Rottmann ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2447
-gerrit commit 970e7cddf1d81e03569c092651c46f4f70e1cd14 Author: Jens Rottmann <[email protected]> Date: Mon Feb 18 20:13:27 2013 +0100 Persimmon: disable APU PCIe port 3 According to DB-FT1 rev. D schematics the APU PCIe lane 3 is unconnected. Reflect this fact in the mainboard code. Change-Id: Ic98f4a63ef971628df7fbf97f56b80ebe7cb8517 Signed-off-by: Jens Rottmann <[email protected]> --- src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index a49be62..89334d9 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -50,7 +50,7 @@ #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
