Jens Rottmann ([email protected]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2572
-gerrit commit 2b8997e47afbacd965a93da1b761f618258e204a Author: Jens Rottmann <[email protected]> Date: Fri Mar 1 17:20:42 2013 +0100 LiPPERT Toucan-AF [2/2]: actually implement mainboard support Step 2: change the Persimmon code to adapt it to the new board's hardware. The Toucan-AF is a COM Express Compact Type 6 form factor embedded board: - AMD Fusion G-T56N (1.65 GHz dual core) or T40R (1 GHz single core) APU - 1-4 GB DDR3 memory down - 1x VGA, 2x DisplayPort (1 switchable to LVDS) - AMD A55E (Hudson-E1) southbridge - 8x USB 2.0 - 4x SATA - HD Audio (with codec on baseboard) - NEC uPD78F0532 microcontroller on I2C ("SEMA") - 7x PCIe2.0 x1 (1 on PEG) - Intel I210 GbE (on APU PCIe x1, can be disabled for additional PCIe) - 2x SST 25VF032B (SO8, soldered) 4 MB SPI flash (BIOS and failsafe BIOS) The Toucan-AF has no SIO on board. This patch includes basic support for a Winbond W83627DHG (PS/2, 2x RS232), because the ADLINK ExpressBase-6 used for evaluation happens to have one. The code may have to be adapted to the actual baseboard of the application. http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 Change-Id: I9041b905bad45852ac9b402fcbd5decbc98b377b Signed-off-by: Jens Rottmann <[email protected]> --- src/mainboard/lippert/Kconfig | 7 +- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 67 ++++-------- src/mainboard/lippert/toucan-af/BiosCallOuts.h | 10 ++ src/mainboard/lippert/toucan-af/Kconfig | 24 +++-- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 10 +- .../lippert/toucan-af/PlatformGnbPcieComplex.h | 2 +- src/mainboard/lippert/toucan-af/acpi/superio.asl | 39 +++++++ src/mainboard/lippert/toucan-af/buildOpts.c | 1 + src/mainboard/lippert/toucan-af/devicetree.cb | 113 +++++++-------------- src/mainboard/lippert/toucan-af/dsdt.asl | 2 + src/mainboard/lippert/toucan-af/mainboard.c | 72 +++++++++++++ src/mainboard/lippert/toucan-af/platform_cfg.h | 40 ++++---- src/mainboard/lippert/toucan-af/romstage.c | 6 +- 13 files changed, 231 insertions(+), 162 deletions(-) diff --git a/src/mainboard/lippert/Kconfig b/src/mainboard/lippert/Kconfig index 8797a14..cf5288e 100644 --- a/src/mainboard/lippert/Kconfig +++ b/src/mainboard/lippert/Kconfig @@ -15,10 +15,12 @@ config BOARD_LIPPERT_ROADRUNNER_LX bool "Cool RoadRunner-LX" config BOARD_LIPPERT_SPACERUNNER_LX bool "Cool SpaceRunner-LX" +config BOARD_LIPPERT_TOUCAN_AF + bool "Toucan-AF (+W83627DHG SIO)" endchoice -if BOARD_LIPPERT_FRONTRUNNER_AF +if BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF # No code, but two Kconfig options need to know this ... choice prompt "AMD Fusion CPU model" @@ -47,7 +49,7 @@ config FUSION_G_T56N If unsure check with "grep model /proc/cpuinfo". endchoice -endif # BOARD_LIPPERT_FRONTRUNNER_AF +endif # BOARD_LIPPERT_FRONTRUNNER_AF || BOARD_LIPPERT_TOUCAN_AF source "src/mainboard/lippert/frontrunner/Kconfig" source "src/mainboard/lippert/frontrunner-af/Kconfig" @@ -55,6 +57,7 @@ source "src/mainboard/lippert/hurricane-lx/Kconfig" source "src/mainboard/lippert/literunner-lx/Kconfig" source "src/mainboard/lippert/roadrunner-lx/Kconfig" source "src/mainboard/lippert/spacerunner-lx/Kconfig" +source "src/mainboard/lippert/toucan-af/Kconfig" config MAINBOARD_VENDOR string diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 9bad4f4..936ce9b 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -22,7 +22,6 @@ #include "dimmSpd.h" #include "BiosCallOuts.h" #include "heapManager.h" -#include "SB800.h" STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { @@ -445,9 +444,25 @@ AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPt /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. - // Make sure the right speed settings are selected. - ((MEM_DATA_STRUCT*)ConfigPtr)->ParameterListPtr->DDR3Voltage = VOLT1_5; + MEM_DATA_STRUCT *MemData = ConfigPtr; + + printk(BIOS_INFO, "Setting DDR3 voltage: "); + FCH_IOMUX(65) = 1; // GPIO65: VMEM_LV_EN# lowers VMEM from 1.5 to 1.35V + switch (MemData->ParameterListPtr->DDR3Voltage) { + case VOLT1_25: // board is not able to provide this + MemData->ParameterListPtr->DDR3Voltage = VOLT1_35; // sorry + printk(BIOS_INFO, "can't provide 1.25 V, using "); + // fall through + default: // AGESA.h says in mixed case 1.5V DIMMs get excluded + case VOLT1_35: + FCH_GPIO(65) = 0x08; // = output, disable PU, set to 0 + printk(BIOS_INFO, "1.35 V\n"); + break; + case VOLT1_5: + FCH_GPIO(65) = 0xC8; // = output, disable PU, set to 1 + printk(BIOS_INFO, "1.5 V\n"); + } + return AGESA_SUCCESS; } @@ -465,45 +480,7 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 46: // GPIO50 = SBGPIO_PCIE_RST# affects LAN0, LAN1, PCIe slot - switch (ResetInfo->ResetControl) { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG50); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG50, Data8); - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; + // COM Express doesn't provide dedicated resets for individual lanes + // and it's not needed for the on-board Intel I210 GbE controller. + return AGESA_UNSUPPORTED; } diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.h b/src/mainboard/lippert/toucan-af/BiosCallOuts.h index c4f4f70..48ee595 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.h +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.h @@ -22,6 +22,7 @@ #include "Porting.h" #include "AGESA.h" +#include "SB800.h" #define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */ #define BIOS_HEAP_SIZE 0x20000 @@ -70,4 +71,13 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* FCH GPIO access helpers */ +#define FCH_IOMUX(gpio_nr) (*(u8*)(ACPI_MMIO_BASE+IOMUX_BASE+(gpio_nr))) +#define FCH_PMIO(reg_nr) (*(u8*)(ACPI_MMIO_BASE+PMIO_BASE+(reg_nr))) +#define FCH_GPIO(gpio_nr) (*(volatile u8*)(ACPI_MMIO_BASE+GPIO_BASE+(gpio_nr))) +static inline u8 fch_gpio_state(unsigned int gpio_nr) +{ + return FCH_GPIO(gpio_nr) >> 7; +} + #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/lippert/toucan-af/Kconfig b/src/mainboard/lippert/toucan-af/Kconfig index f3f9aa9..72e6a3b 100644 --- a/src/mainboard/lippert/toucan-af/Kconfig +++ b/src/mainboard/lippert/toucan-af/Kconfig @@ -17,7 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_AMD_PERSIMMON +if BOARD_LIPPERT_TOUCAN_AF config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -26,11 +26,17 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14_ROOT_COMPLEX select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 - select SUPERIO_FINTEK_F81865F + # The Toucan-AF is meant to work on any COM Express Type 6 baseboard. + # The ADLINK ExpressBase-6 baseboard happens to use this SIO: + select SUPERIO_WINBOND_W83627DHG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME + # S3 doesn't work yet, heapManager.c:576 failed last time I tried, + # couldn't figure out why. But s3_resume.c (look for "spi_flash_probe") + # erases 28 KB and writes 10 KB register dumps to SPI flash on every + # boot, wasting 3 s and causing wear! Therefore disable S3 for now. + #select HAVE_ACPI_RESUME select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID @@ -42,7 +48,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy config MAINBOARD_DIR string - default amd/persimmon + default lippert/toucan-af config APIC_ID_OFFSET hex @@ -50,7 +56,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "Persimmon" + default "Toucan-AF" config HW_MEM_HOLE_SIZEK hex @@ -58,7 +64,8 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 2 + default 1 if FUSION_G_T40R + default 2 if FUSION_G_T56N config MAX_PHYSICAL_CPUS int @@ -111,7 +118,8 @@ config VGA_BIOS config VGA_BIOS_ID string - default "1002,9802" + default "1002,9804" if FUSION_G_T40R + default "1002,9806" if FUSION_G_T56N config SB800_AHCI_ROM bool @@ -121,4 +129,4 @@ config DRIVERS_PS2_KEYBOARD bool default n -endif # BOARD_AMD_PERSIMMON +endif # BOARD_LIPPERT_TOUCAN_AF diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index 14839c7..ea59c44 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -60,19 +60,19 @@ PCIe_PORT_DESCRIPTOR PortList [] = { { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { @@ -94,14 +94,14 @@ PCIe_DDI_DESCRIPTOR DdiList [] = { 0, //Descriptor flags PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeLvds, Aux1, Hdp1} + {ConnectorTypeAutoDetect, Aux1, Hdp1} }, // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) { DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} + {ConnectorTypeAutoDetect, Aux2, Hdp2} } }; diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index ec8a6e3..69e2615 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -50,7 +50,7 @@ #define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced //GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 0 //0:Disable 1:Enable +#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable #define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 #define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 #define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) diff --git a/src/mainboard/lippert/toucan-af/acpi/superio.asl b/src/mainboard/lippert/toucan-af/acpi/superio.asl new file mode 100644 index 0000000..9be7492 --- /dev/null +++ b/src/mainboard/lippert/toucan-af/acpi/superio.asl @@ -0,0 +1,39 @@ +/* + * SuperI/O devices + * + * This file is part of the coreboot project. + * + * Copyright (C) 2012 LiPPERT ADLINK Technology GmbH + * (Written by Jens Rottmann <[email protected]> for LiPPERT) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* PS/2 Keyboard */ +Device(KBC) { + Name(_HID, EISAID("PNP0303")) + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0060, 0x0060, 1, 1) + IO(Decode16, 0x0064, 0x0064, 1, 1) + IRQNoFlags(){1} + }) +} + +/* PS/2 Mouse */ +Device(PS2M) { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){12} + }) +} diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index c6383a2..45ffac6 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -385,6 +385,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // Byte6Seed, Byte7Seed, ByteEccSeed) // Specifies the write leveling seed for a channel of a socket. // + HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B), NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), PSO_END diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index d108a11..fbe2a2c 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -29,10 +29,11 @@ chip northbridge/amd/agesa/family14/root_complex chip northbridge/amd/agesa/family14 # PCI side of HT root complex device pci 0.0 on end # Root Complex device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge + #device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge on-board NIC device pci 8.0 off end # NB/SB Link P2P bridge end # agesa northbridge @@ -47,97 +48,51 @@ chip northbridge/amd/agesa/family14/root_complex device i2c 50 on end end chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device i2c 51 off end end end # SM - device pci 14.1 on end # IDE 0x439c + device pci 14.1 off end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 + chip superio/winbond/w83627dhg + device pnp 4e.0 off end # Floppy + device pnp 4e.1 off end # Parallel Port + device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.11 on # COM2 + device pnp 4e.3 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - end # f81865f + device pnp 4e.5 on # Keyboard, Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 4e.6 off end # SPI + device pnp 4e.307 off end # GPIO6 + device pnp 4e.8 off end # WDTO, PLED + device pnp 4e.009 off end # GPIO2 + device pnp 4e.109 off end # GPIO3 + device pnp 4e.209 off end # GPIO4 + device pnp 4e.309 off end # GPIO5 + device pnp 4e.A off end # ACPI + device pnp 4e.B off end # HW Monitor + end # w83627dhg end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} device pci 14.5 off end # OHCI FS/LS USB device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB + device pci 15.2 on end # PCIe PortC + device pci 15.3 on end # PCIe PortD device pci 16.0 off end # OHCI USB 10-13 device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "gpp_configuration" = "4" #1:1:1:1 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" - - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" - end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 582ab7f..cde41b4 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1462,6 +1462,7 @@ DefinitionBlock ( } } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ #endif + #include "acpi/superio.asl" } /* end LIBR */ Device(HPBR) { @@ -1477,6 +1478,7 @@ DefinitionBlock ( } /* end Ac97modem */ Name(CRES, ResourceTemplate() { + IO(Decode16, 0x004E, 0x004E, 1, 2) /* SIO config regs */ IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, diff --git a/src/mainboard/lippert/toucan-af/mainboard.c b/src/mainboard/lippert/toucan-af/mainboard.c index 99e1c30..27952fa 100644 --- a/src/mainboard/lippert/toucan-af/mainboard.c +++ b/src/mainboard/lippert/toucan-af/mainboard.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -29,6 +30,76 @@ #include <cpu/amd/agesa/s3_resume.h> #include <cpu/amd/mtrr.h> #include "SBPLATFORM.h" +#include "OEM.h" /* SMBUS0_BASE_ADDRESS */ + +/* Write data block to slave on SMBUS0. */ +#define SMB0_STATUS ((SMBUS0_BASE_ADDRESS) + 0) +#define SMB0_CONTROL ((SMBUS0_BASE_ADDRESS) + 2) +#define SMB0_HOSTCMD ((SMBUS0_BASE_ADDRESS) + 3) +#define SMB0_ADDRESS ((SMBUS0_BASE_ADDRESS) + 4) +#define SMB0_DATA0 ((SMBUS0_BASE_ADDRESS) + 5) +#define SMB0_BLOCKDATA ((SMBUS0_BASE_ADDRESS) + 7) +static int smb_write_blk(u8 slave, u8 command, u8 length, const u8 *data) +{ + __outbyte(SMB0_STATUS, 0x1E); // clear error status + __outbyte(SMB0_ADDRESS, slave & ~1); // slave addr + direction=out + __outbyte(SMB0_HOSTCMD, command); // or destination offset + __outbyte(SMB0_DATA0, length); // sent before data + __inbyte(SMB0_CONTROL); // reset block data array + while (length--) + __outbyte(SMB0_BLOCKDATA, *(data++)); + __outbyte(SMB0_CONTROL, 0x54); // execute block write, no IRQ + + while (__inbyte(SMB0_STATUS) == 0x01) ; // busy, no errors + return __inbyte(SMB0_STATUS) ^ 0x02; // 0x02 = completed, no errors +} + +static void init(struct device *dev) +{ + int i; + printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " ENTER %s\n", __func__); + + /* Init Hudson GPIOs. */ + printk(BIOS_DEBUG, "Init FCH GPIOs @ 0x%08x\n", ACPI_MMIO_BASE+GPIO_BASE); + FCH_IOMUX( 50) = 2; // GPIO50: FCH_ARST#_GATE resets stuck PCIe devices + FCH_GPIO ( 50) = 0xC0; // = output set to 1 as it's never needed + FCH_IOMUX(197) = 2; // GPIO197: BIOS_DEFAULTS# + FCH_GPIO (197) = 0x28; // = input, disable int. pull-up + FCH_IOMUX( 56) = 1; // GPIO58-56: REV_ID2-0 + FCH_GPIO ( 56) = 0x28; // = inputs, disable int. pull-ups + FCH_IOMUX( 57) = 1; + FCH_GPIO ( 57) = 0x28; + FCH_IOMUX( 58) = 1; + FCH_GPIO ( 58) = 0x28; + FCH_IOMUX(187) = 2; // GPIO187,188,166,GPO160: GPO0-3 on COM Express connector + FCH_GPIO (187) = 0x08; // = outputs, disable PUs, default to 0 + FCH_IOMUX(188) = 2; + FCH_GPIO (188) = 0x08; + FCH_IOMUX(166) = 2; + FCH_GPIO (166) = 0x08; + // needed to make GPO160 work (Hudson Register Reference section 2.3.6.1) + FCH_PMIO(0xDC) &= ~0x80; FCH_PMIO(0xE6) = (FCH_PMIO(0xE6) & ~0x02) | 0x01; + FCH_IOMUX(160) = 1; + FCH_GPIO (160) = 0x08; + FCH_IOMUX(189) = 1; // GPIO189-192: GPI0-3 on COM Express connector + FCH_IOMUX(190) = 1; // default to inputs with int. PU + FCH_IOMUX(191) = 1; + FCH_IOMUX(192) = 1; + if (!fch_gpio_state(197)) // just in case anyone cares + printk(BIOS_INFO, "BIOS_DEFAULTS jumper is present.\n"); + printk(BIOS_INFO, "Board revision ID: %u\n", + fch_gpio_state(58)<<2 | fch_gpio_state(57)<<1 | fch_gpio_state(56)); + + /* Notify the SMC we're alive and kicking, or after a while it will + * effect a power cycle and switch to the alternate BIOS chip. + * Should be done as late as possible. */ + printk(BIOS_INFO, "Sending BIOS alive message\n"); + const u8 i_am_alive[] = { 0x03 }; //bit2=SEL_DP0: 0=DDI2, 1=LVDS + if ((i = smb_write_blk(0x50, 0x25, sizeof(i_am_alive), i_am_alive))) + printk(BIOS_ERR, "smb_write_blk failed: %d\n", i); + + printk(BIOS_DEBUG, CONFIG_MAINBOARD_PART_NUMBER " EXIT %s\n", __func__); +} void set_pcie_reset(void); void set_pcie_dereset(void); @@ -56,6 +127,7 @@ void set_pcie_dereset(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + dev->ops->init = init; /* * The mainboard is the first place that we get control in ramstage. Check diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index b0ac180..3c09713 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -77,7 +77,7 @@ * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 */ -#define USB_CONFIG 0x7F +#define USB_CONFIG 0x0F /** * @def PCI_CLOCK_CTRL @@ -90,7 +90,7 @@ * PCI SLOT 3 define at BIT3 * PCI SLOT 4 define at BIT4 */ -#define PCI_CLOCK_CTRL 0x07 +#define PCI_CLOCK_CTRL 0x1E /** * @def SATA_CONTROLLER @@ -180,7 +180,6 @@ * SDIN2 is define at BIT4 & BIT5 * SDIN3 is define at BIT6 & BIT7 */ -//#define AZALIA_SDIN_PIN 0xAA #define AZALIA_SDIN_PIN 0x2A /** @@ -225,29 +224,32 @@ * 0 - Enable * 1 - Disable */ -#define GEC_CONFIG 0 +#define GEC_CONFIG 1 -static const CODECENTRY persimmon_codec_alc269[] = +static const CODECENTRY sample_codec_alc886[] = /* Realtek ALC886/8 */ { - /* NID, PinConfig */ - {0x12, 0x411111F0}, - {0x14, 0x99130110}, - {0x21, 0x0121401F}, - {0x17, 0x411111F0}, - {0x18, 0x01A19820}, - {0x19, 0x411111F0}, - {0x1A, 0x0181302F}, - {0x1B, 0x411111F0}, - {0x1D, 0x40069E05}, - {0x1E, 0x411111F0}, - {0x20, 0x0001FFFF}, + /* NID, PinConfig (Verbs 71F..C) */ + {0x11, 0x411111F0}, /* NPC */ + {0x12, 0x411111F0}, /* DMIC */ + {0x14, 0x01214110}, /* FRONT (Port-D) */ + {0x15, 0x01011112}, /* SURR (Port-A) */ + {0x16, 0x01016111}, /* CEN/LFE (Port-G) */ + {0x17, 0x411111F0}, /* SIDESURR (Port-H) */ + {0x18, 0x01A19930}, /* MIC1 (Port-B) */ + {0x19, 0x411111F0}, /* MIC2 (Port-F) */ + {0x1A, 0x0181313F}, /* LINE1 (Port-C) */ + {0x1B, 0x411111F0}, /* LINE2 (Port-E) */ + {0x1C, 0x411111F0}, /* CD-IN */ + {0x1D, 0x40132601}, /* BEEP-IN */ + {0x1E, 0x01441120}, /* S/PDIF-OUT */ + {0x1F, 0x01C46140}, /* S/PDIF-IN */ {0xff, 0xffffffff} /* end of table */ }; static const CODECTBLLIST codec_tablelist[] = { - {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, - {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} + {0x10ec0888, (CODECENTRY*)&sample_codec_alc886[0]}, + {0xFFFFFFFF, (CODECENTRY*)0xFFFFFFFFL} }; /** diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 2ed4a77..7d11813 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -31,7 +31,7 @@ #include <console/loglevel.h> #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "superio/fintek/f81865f/f81865f_early_serial.c" +#include "superio/winbond/w83627dhg/w83627dhg.h" #include "cpu/x86/lapic/boot_cpu.c" #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" @@ -45,7 +45,7 @@ void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -70,7 +70,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); post_code(0x31); - f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
