On Wed, Apr 10, 2013 at 09:37:34AM +0200, Paul Menzel wrote: > Dear yili0568, > > > please do not top post but use interleaved style instead [1]. I'm sorry. > > Am Mittwoch, den 10.04.2013, 15:04 +0800 schrieb yili0...@gmail.com: > > Thanks. And I found the comment > > "/* > > * Set registers in RS780 and CPU to enable the internal GFX. > > * Please refer to CIM source code and BKDG. > > */" > > from the file Targets/Bonito3a780e/pci/rs780_gfx.c, > > Where do you get this source tree from? It does not look like our > upstream coreboot tree? Searching for »Bonito3a780e«, do you develop a > Lemote device [2][3]? This is great news when this is true and Lemote is > using coreboot! > Both lemote and loongson[1] is using pmon, in which a lot of codes ported from coreboot. > > where is CIM source code? > > $ find . -type d -iname '*cim*' > ./src/northbridge/amd/cimx > ./src/southbridge/amd/cimx > ./src/vendorcode/amd/cimx > ./build/southbridge/amd/cimx > ./build/vendorcode/amd/cimx > $ ls src/southbridge/amd/cimx/ > cimx_util.c cimx_util.h Kconfig Makefile.inc sb700 sb800 sb900 >
> > [1] http://en.opensuse.org/openSUSE:Mailing_list_netiquette > [2] > http://dev.lemote.com/cgit/pmon.git/tree/Targets/Bonito3a780e/conf/files.Bonito3a780e?id=b57ea5c717235643e8490ec3131eb45111b0c371 > [3] http://dev.lemote.com/cgit/pmon.git/tree/Targets/ Thanks, I've find the cimx, and there is another question. I've configured the rs780e's gfx as 2 x8 bridges(dev2 and dev3 of bus0), after link trained both dev2 and dev3 are x8. >From the function PcieTrainPort: case 0x06: /* read back current link width [6:4]. */ current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7; /* 4 means 7:4 and 15:12 * 3 means 7:2 and 15:10 * 2 means 7:1 and 15:9 * egnoring the reversal case */ lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF; reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel); reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); set_pcie_dereset(); break; I've print the current_link_width, both dev2 and dev3 print 4. Does 4 means x8? Then I boot linux lspci -vvv 00:02.0 ...... LnkCap: Port #0, Speed 5GT/s, Width x8,...... ...... LnkSta: Speed 2.5GT/s, Width x2,...... It is the same to the dev3. The cb file is from src/mainboard/amd/mahogany_fam10/devicetree.cb Do you know about the link tranning of gfx of rs780e? Thanks. [1] http://www.loongson.cn/dev/gitweb/?p=pmon-loongson3;a=summary -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
