Dear coreboot folks,
Am Freitag, den 12.04.2013, 14:35 +0200 schrieb Paul Menzel: > investigating, why GRUB is not able to find my SATA drive when the SATA > controller is in AHCI mode [1], Vladimir pointed out that the controller > does not advertise support of staggered spin-up as described in section > 10.10 of the AHCI specification [2]. > > Looking at the SeaBIOS serial log with the debug level set to 8, the > flags are printed as follows. > > AHCI: cap 0xf332ff05, ports_impl 0x3f > > With the following SeaBIOS code > > $ nl -ba src/ahci.h > […] > 97 /* global controller registers */ > 98 #define HOST_CAP 0x00 /* host capabilities */ > […] > 109 /* HOST_CAP bits */ > 110 #define HOST_CAP_SSC (1 << 14) /* Slumber > capable */ > 111 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */ > 112 #define HOST_CAP_CLO (1 << 24) /* Command List > Override support */ > 113 #define HOST_CAP_SSS (1 << 27) /* Staggered > Spin-up */ > […] > $ nl -ba src/ahci.c > […] > 601 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP); > 602 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL); > 603 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n", > 604 ctrl->caps, ctrl->ports); > […] > > this means, that for `HOST_CAP_SSS` we have to look at the 7th digit > from the right of the hex number 0xf332ff05, which is 3, which is in > 0011b, and now at the fourth digit from the right which is 0. So this is > disabled. (SeaBIOS does not seem to care about the flag though.) I forgot to add, that I looked at the Register Reference Guide (RRG) and Register Programming Requirements (RPR) [4] and have the impression that staggered spin-up is supported by the hardware. > Reading the code in `src/vendorcode/amd/cimx/sb800/SATA.c` [3] I do not > find where this bit might be set. > > So any idea, why the CIMx code does not allow to enable staggered > spin-up? Are there known problems with the hardware or is it just not > implemented in CIMx yet and should simply be added? Thanks, Paul > [1] http://lists.gnu.org/archive/html/grub-devel/2013-04/msg00058.html > [2] > http://www.intel.com/content/www/us/en/io/serial-ata/serial-ata-ahci-spec-rev1_3.html > [3] > http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/cimx/sb800/vendorcode/amd/cimx/sb800/SATA.c;h=b7bbacdbdb84992f8761aeb215e29abd385ff2f7;hb=HEAD#l346 [4] http://www.coreboot.org/Datasheets#AMD_SB800
signature.asc
Description: This is a digitally signed message part
-- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
