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Hash: SHA1
Hi,
The fact that my M4A785T-M got unusable with master
pushed me to retest that patch:
23:58 < PaulePanter> GNUtoo-irssi: git fetch
http://review.coreboot.org/coreboot refs/changes/41/4541/1 && git
checkout FETCH_HEAD
So instead of doing a checkout, I did a cherry-pick of the patch on top
of master, and I've attached the log.
I don't remember what happened but we probably deadlocked each other.
What probably happened is that you wrote a mail to the mailing list,
which I didn't respond to because I responded trough IRC.
I probably didn't even see the thread because with my mali setup, the
coreboot mails are now automatically in a coreboot folder, and since I
don't work on it right now, I probably didn't look it up.
M4A785T-M status:
- -----------------
Here is the difference of status since I touched it last time(probably
about one year ago). The new status of the M4A785T-M is on top of a
patched old master.
* The mmconf issues are still there on master
* Ram init got very unstable lately, lately I have freeze once booted,
and before I had difficult boot (sometimes it reseted during the
boot).
* 4G of RAM doesn't work, most probably because of the unstable RAM
init, because it has the same reboot symptom, but way more frequently.
* The sound card now works!
Denis.
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gnutoo@X60 ~ % picocom -b 115200 /dev/ttyUSB0
picocom v1.7
port is : /dev/ttyUSB0
flowcontrol : none
baudrate is : 115200
parity is : none
databits are : 8
escape is : C-a
local echo is : no
noinit is : no
noreset is : no
nolock is : no
send_cmd is : sz -vv
receive_cmd is : rz -vv
imap is :
omap is :
emap is : crcrlf,delbs,
Terminal ready
coreboot-4.0-6222-g4312dde Sat Jun 14 00:17:54 CEST 2014 starting...
BSP Family_Model: 00100f62
*sysinfo range: [000c4000,000c7360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1062, current patch id = 0x00000000
microcode: patch id to apply = 0x0100009f
microcode: updated to patch id = 0x0100009f success
cpuSetAMDMSR done
Enter amd_ht_init()
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600e681
F3x84: 80e641e6
F3xD4: c8810f24
F3xD8: 03001016
F3xDC: 0000532a
core0 started:
start_other_cores()
init node: 00 cores: 01
Start other core - nodeid: 00 cores: 01
started ap apicid: * AP 01started
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x30bc0073 0x44035440
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c005440
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
...WARM RESET...
coreboot-4.0-6222-g4312dde Sat Jun 14 00:17:54 CEST 2014 starting...
BSP Family_Model: 00100f62
*sysinfo range: [000c4000,000c7360]
bsp_apicid = 00
cpu_init_detectedx = 00000000
microcode: equivalent rev id = 0x1062, current patch id = 0x00000000
microcode: patch id to apply = 0x0100009f
microcode: updated to patch id = 0x0100009f success
cpuSetAMDMSR done
Enter amd_ht_init()
Exit amd_ht_init()
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600e681
F3x84: 80e641e6
F3xD4: c8810f26
F3xD8: 03001016
F3xDC: 0000532a
core0 started:
start_other_cores()
init node: 00 cores: 01
Start other core - nodeid: 00 cores: 01
started ap apicid: * AP 01started
rs780_early_setup()
fam10_optimization()
rs780_por_init
sb700_early_setup()
sb700_devices_por_init()
sb700_devices_por_init(): SMBus Device, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x30bc0073 0x3c005440
End FIDVIDMSR 0xc0010071 0x30bc0073 0x3c001c0e
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
fill_mem_ctrl()
raminit_amdmct()
raminit_amdmct begin:
DIMMPresence: DIMMValid=1
DIMMPresence: DIMMPresent=1
DIMMPresence: RegDIMMPresent=0
DIMMPresence: DimmECCPresent=0
DIMMPresence: DimmPARPresent=0
DIMMPresence: Dimmx4Present=0
DIMMPresence: Dimmx8Present=1
DIMMPresence: Dimmx16Present=0
DIMMPresence: DimmPlPresent=0
DIMMPresence: DimmDRPresent=1
DIMMPresence: DimmQRPresent=0
DIMMPresence: DATAload[0]=2
DIMMPresence: MAload[0]=10
DIMMPresence: MAdimms[0]=1
DIMMPresence: DATAload[1]=0
DIMMPresence: MAload[1]=0
DIMMPresence: MAdimms[1]=0
DIMMPresence: Status 1000
DIMMPresence: ErrStatus 0
DIMMPresence: ErrCode 0
DIMMPresence: Done
DCTInit_D: mct_DIMMPresence Done
SPDCalcWidth: Status 1000
SPDCalcWidth: ErrStatus 0
SPDCalcWidth: ErrCode 0
SPDCalcWidth: Done
DCTInit_D: mct_SPDCalcWidth Done
SPDGetTCL_D: DIMMCASL 4
SPDGetTCL_D: DIMMAutoSpeed 4
SPDGetTCL_D: Status 1000
SPDGetTCL_D: ErrStatus 0
SPDGetTCL_D: ErrCode 0
SPDGetTCL_D: Done
AutoCycTiming: Status 1000
AutoCycTiming: ErrStatus 0
AutoCycTiming: ErrCode 0
AutoCycTiming: Done
DCTInit_D: AutoCycTiming_D Done
SPDSetBanks: CSPresent 3
SPDSetBanks: Status 1000
SPDSetBanks: ErrStatus 0
SPDSetBanks: ErrCode 0
SPDSetBanks: Done
AfterStitch pDCTstat->NodeSysBase = 0
mct_AfterStitchMemory: pDCTstat->NodeSysLimit = 7fffff
StitchMemory: Status 1000
StitchMemory: ErrStatus 0
StitchMemory: ErrCode 0
StitchMemory: Done
InterleaveBanks_D: Status 1000
InterleaveBanks_D: ErrStatus 0
InterleaveBanks_D: ErrCode 0
InterleaveBanks_D: Done
AutoConfig_D: DramControl: 2a06
AutoConfig_D: DramTimingLo: 90092
AutoConfig_D: DramConfigMisc: 0
AutoConfig_D: DramConfigMisc2: 0
AutoConfig_D: DramConfigLo: 8010000
AutoConfig_D: DramConfigHi: f48000b
AutoConfig: Status 1000
AutoConfig: ErrStatus 0
AutoConfig: ErrCode 0
AutoConfig: Done
DCTInit_D: AutoConfig_D Done
DCTInit_D: PlatformSpec_D Done
DCTInit_D: StartupDCT_D
mctAutoInitMCT_D: SyncDCTsReady_D
mctAutoInitMCT_D: HTMemMapInit_D
Node: 00 base: 00 limit: 7fffff BottomIO: c00000
Node: 00 base: 03 limit: 7fffff
Node: 01 base: 00 limit: 00
Node: 02 base: 00 limit: 00
Node: 03 base: 00 limit: 00
Node: 04 base: 00 limit: 00
Node: 05 base: 00 limit: 00
Node: 06 base: 00 limit: 00
Node: 07 base: 00 limit: 00
mctAutoInitMCT_D: CPUMemTyping_D
CPUMemTyping: Cache32bTOP:800000
CPUMemTyping: Bottom32bIO:800000
CPUMemTyping: Bottom40bIO:0
mctAutoInitMCT_D: DQSTiming_D
vErrata350: dummy read
vErrata350: dummy read
vErrata350: dummy read
vErrata350: dummy read
vErrata350: step 2a
vErrata350: step 2b
vErrata350: step 3
vErrata350: step 4
vErrata350: step 4b
vErrata350: step 5
TrainRcvrEn: Status 1000
TrainRcvrEn: ErrStatus 0
TrainRcvrEn: ErrCode 0
TrainRcvrEn: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
TrainDQSRdWrPos: Status 1000
TrainDQSRdWrPos: TrainErrors 0
TrainDQSRdWrPos: ErrStatus 0
TrainDQSRdWrPos: ErrCode 0
TrainDQSRdWrPos: Done
mctAutoInitMCT_D: UMAMemTyping_D
mctAutoInitMCT_D: :OtherTiming
InterleaveNodes_D: Status 1000
InterleaveNodes_D: ErrStatus 0
InterleaveNodes_D: ErrCode 0
InterleaveNodes_D: Done
InterleaveChannels_D: Node 0
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 1
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 2
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 3
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 4
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 5
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 6
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Node 7
InterleaveChannels_D: Status 1000
InterleaveChannels_D: ErrStatus 0
InterleaveChannels_D: ErrCode 0
InterleaveChannels_D: Done
mctAutoInitMCT_D: ECCInit_D
ECCInit: Node 00
ECCInit: Status 1000
ECCInit: ErrStatus 0
ECCInit: ErrCode 0
ECCInit: Done
mctAutoInitMCT_D Done: Global Status: 0
raminit_amdmct end:
v_esp=000cfee8
Copying data from cache to RAM -- switching to use RAM as stack... Done
Disabling cache as ram now
Clearing initial memory region: Done
Trying CBFS ramstage loader.
CBFS: loading stage fallback/ramstage @ 0x200000 (1101872 bytes), entry @ 0x200000
WARNING: you need to define get_top_of_ram() for your chipset
WARNING: you need to define get_top_of_ram() for your chipset
WARNING: you need to define get_top_of_ram() for your chipset
ERROR: failed to allocate timestamp table
coreboot-4.0-6222-g4312dde Sat Jun 14 00:17:54 CEST 2014 booting...
BS: Entering BS_PRE_DEVICE state.
BS: Exiting BS_PRE_DEVICE state.
BS: Entering BS_DEV_INIT_CHIPS state.
BS: Exiting BS_DEV_INIT_CHIPS state.
BS: Entering BS_DEV_ENUMERATE state.
Enumerating buses...
Show all devs...Before device enumeration.
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:05.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Compare with tree...
Root Device: enabled 1
CPU_CLUSTER: 0: enabled 1
APIC: 00: enabled 1
DOMAIN: 0000: enabled 1
PCI: 00:18.0: enabled 1
PCI: 00:00.0: enabled 1
PCI: 00:01.0: enabled 1
PCI: 00:05.0: enabled 1
PCI: 00:02.0: enabled 1
PCI: 00:03.0: enabled 0
PCI: 00:04.0: enabled 0
PCI: 00:05.0: enabled 0
PCI: 00:06.0: enabled 0
PCI: 00:07.0: enabled 0
PCI: 00:08.0: enabled 0
PCI: 00:09.0: enabled 0
PCI: 00:0a.0: enabled 1
PCI: 00:11.0: enabled 1
PCI: 00:12.0: enabled 1
PCI: 00:12.1: enabled 1
PCI: 00:12.2: enabled 1
PCI: 00:13.0: enabled 1
PCI: 00:13.1: enabled 1
PCI: 00:13.2: enabled 1
PCI: 00:14.0: enabled 1
I2C: 00:50: enabled 1
I2C: 00:51: enabled 1
I2C: 00:52: enabled 1
I2C: 00:53: enabled 1
PCI: 00:14.1: enabled 1
PCI: 00:14.2: enabled 1
PCI: 00:14.3: enabled 1
PNP: 002e.0: enabled 0
PNP: 002e.1: enabled 1
PNP: 002e.2: enabled 0
PNP: 002e.3: enabled 0
PNP: 002e.4: enabled 0
PNP: 002e.5: enabled 1
PNP: 002e.6: enabled 1
PNP: 002e.7: enabled 0
PNP: 002e.8: enabled 0
PNP: 002e.9: enabled 0
PNP: 002e.a: enabled 0
PCI: 00:14.4: enabled 1
PCI: 00:14.5: enabled 1
PCI: 00:18.1: enabled 1
PCI: 00:18.2: enabled 1
PCI: 00:18.3: enabled 1
PCI: 00:18.4: enabled 1
Mainboard enable. dev=0x0022b0c4
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
Init adt7461 end , status 0x02 fd
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
Switched MMCONF to IO on PCI: 00:14.0
scan_static_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
setup_uma_memory: uma size 0x10000000, memory start 0x70000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
PCI: 00:18.3 siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:18.0 [1022/1200] bus ops
PCI: 00:18.0 [1022/1200] enabled
PCI: 00:18.1 [1022/1201] enabled
PCI: 00:18.2 [1022/1202] enabled
PCI: 00:18.3 [1022/1203] ops
PCI: 00:18.3 [1022/1203] enabled
PCI: 00:18.4 [1022/1204] enabled
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
rs780_enable: dev=0022b920, VID_DID=0x96011022
Bus-0, Dev-0, Fun-0.
enable_pcie_bar3()
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
Switched MMCONF to IO on PCI: 00:00.0
--
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