hi, i did some experiments with the baytrail fsp coreboot and first of all i like to say thanks for all the good code! everything looks much better than the last time i tried to do anything with coreboot.
for the problems - maybe there is something wrong with reading the ids. i found that on my platform it seems like fsp is change mmio base address. so pci reads will not work there after and read all ff. maybe there should be a check which reads back mmio and does some debug log. a example for access to the base address is in setup_mmconfig regards, 2014-06-20 12:33 GMT+02:00 Mike Hibbett <mhibb...@ircona.com>: > > PCI ids will be different > > > > Oh - what do you mean by the Sean? > > > > I am still trying to understand why for two identical CPUID/Stepping > E3815s, with the same 8BM flash image, I get different PCI device ids for > the Soc Transaction Router ( 0000 rather than 0f00 ) and Video ( 0031 > rather than 0f00 ). Is this related? > > > > I’ve asked Intel Premier Support but heard nothing back yet. Still puzzled > :o) > > > > Mike. > > > > *From:* coreboot [mailto:coreboot-boun...@coreboot.org] *On Behalf Of *Sean > McNeil > *Sent:* 20 June 2014 11:26 > *To:* Gerald Otter > *Cc:* Wen Wang; coreboot > > *Subject:* Re: [coreboot] latest baytrail fsp on CRB > > > > PCI ids will be different. Plus some devices may be disabled. > > On Jun 20, 2014 5:21 PM, "Gerald Otter" <gerald.ot...@gmail.com> wrote: > > As Mike mentioned earlier, you need the TXE ( located in top 6MB ) from > BYT-I_SEC_DUAL_BOOT_PV_GOLD. > > The TXE from the BIOS’s you mentioned don’t work with coreboot. I ran into > the same issue as you. > > Alternatively you can erase the top 6MB to start in non-descriptor mode. I > don’t think this matters much for coreboot’s startup process, but could be > wrong. > > > > Gerald > > > > On 19 Jun 2014, at 23:08, Wen Wang <wen.w...@adiengineering.com> wrote: > > > > I went back to the commit (Martin’s commit > d75800c7f2476bee243cc22255acb54d6676d4bc back in late May) that seems work > for a few people on the list. I also thought it was working better for me > too as I was observing coreboot and fsp booting until it failed at SeaBIOS. > It turned out I had a pilot error flashing the image. I thought I flashed > the top 2M of the flash, but my script accidentally erased the bottom 6M. > Surprisingly it booted quite far. Anyhow, after I corrected my script > today (flashing only the top 2M, leaving rest from BIOS). Nothing happens, > port 80 remains 0, no console output. Here is cbfstool print, my config > file is attached to an earlier post, > > > > [wenwang@localhost coreboot]$ build/cbfstool build/coreboot.rom print > > coreboot.rom: 2048 kB, bootblocksize 1024, romsize 2097152, offset 0x0 > > alignment: 64 bytes > > > > Name Offset Type Size > > cmos_layout.bin 0x0 cmos_layout 1132 > > pci8086,0f31.rom 0x4c0 optionrom 65536 > > fallback/romstage 0x10500 stage 27029 > > fallback/ramstage 0x16f00 stage 58966 > > fallback/payload 0x255c0 payload 59949 > > config 0x34040 raw 4239 > > (empty) 0x35100 null 896728 > > cpu_microcode_blob.bin 0x110000 microcode 52224 > > (empty) 0x11cc40 null 209752 > > mrc.cache 0x14ffc0 (unknown) 65536 > > (empty) 0x160000 null 393112 > > fsp.bin 0x1bffc0 (unknown) 229376 > > (empty) 0x1f8000 null 31640 > > > > Could it be my BIOS issue? I tried both 64 and 32-bit BIOS from > 540469_540469_BYT_l_66_41_ReleasePackage and > 543844_543844_BYTI_080_011_ReleasePackage. None of them works with my > coreboot build. . Can somebody please share the working BIOS version? > > > > Thanks, > > > > Wen > > > > > > *From:* Mike Hibbett [mailto:mhibb...@ircona.com <mhibb...@ircona.com>] > *Sent:* Wednesday, June 18, 2014 4:58 PM > *To:* Wen Wang; Mike Hibbett; coreboot@coreboot.org > *Subject:* Re: [coreboot] latest baytrail fsp on CRB > > > > Use the one that came with your board, or get the latest From the IBL. I > forget the document number but the file is called > byt-i_sec_dual_boot_pv_gold > > Mike > > Sent with AquaMail for Android > http://www.aqua-mail.com > > On 18 June 2014 21:15:51 Wen Wang <wen.w...@adiengineering.com> wrote: > > .config file attached. > > > > Also what should I do for flash descriptor? > > > > Thanks, > > > > Wen > > > > *From:* Mike Hibbett [mailto:mhibb...@ircona.com <mhibb...@ircona.com>] > *Sent:* Wednesday, June 18, 2014 2:29 PM > *To:* Wen Wang; coreboot@coreboot.org > *Subject:* Re: [coreboot] latest baytrail fsp on CRB > > > > Can you post your coreboot .config file? > > I'm booting bayley bay with a b3 e3815. > > Mike > > Sent with AquaMail for Android > http://www.aqua-mail.com > > On 18 June 2014 19:13:49 Wen Wang <wen.w...@adiengineering.com> wrote: > > Hi all, > > > > Has anybody been able to boot Bayley Bay CRB with the latest coreboot > source from the git tree? We have a Bayley Bay CRB (E3827, B3). With > coreboot Baytrail fsp support pulled from about two weeks ago and some help > from Martin, I was able to see coreboot booting and fsp loaded, but was > having issues with SeaBIOS. I pulled latest source tree this morning and > found out it does not boot any more on my board. Port 80 stuck at code > 0x43, no console output. > > > > Here are my steps: > > 1. Build coreboot toolchain. > > 2. Build coreboot.rom using fsp and microcode from > BAY_TRAIL_FSP_KIT downloaded from Intel fsp site. > > 3. Flash coreboot.rom to top 2M of the 8M flash. > > > > I was getting the usage information here and there from the discussion > threads and perhaps I missed something? It would be great if somebody could > post the detailed procedure. > > > > Thanks! > > > > Wen > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >
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