I found coreboot for AMD Mahogany Fam10 is no longer working. The problem
starts with this change:
http://www.coreboot.org/pipermail/coreboot-gerrit/2013-July/002391.html
Some other older AMD boards are likely affected too. Here is a workaround:
src/device/pci_ops.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c
index 6ddb493..22bd0b1 100644
--- a/src/device/pci_ops.c
+++ b/src/device/pci_ops.c
@@ -27,7 +27,7 @@
const struct pci_bus_operations *pci_bus_default_ops(device_t dev)
{
-#if CONFIG_MMCONF_SUPPORT_DEFAULT
+#if CONFIG_MMCONF_SUPPORT_DEFAULT && CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 0
return &pci_ops_mmconf;
#else
return &pci_cf8_conf1;
--
The public version of AMD simnow (4.6.2) can boot Mahogany FAM10 coreboot
using the included shiner model. But the following patch is needed to
work around a simnow problem that exposes a coreboot problem:
src/device/pci_device.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index 8351e9c..c384877 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -228,6 +228,13 @@ struct resource *pci_get_resource(struct device *dev,
unsigned long index)
* This also catches the common case of unimplemented registers
* that always read back as 0.
*/
+
+ // simnow workaround: clearing NB_BAR3_PCIEXP_ENABLE makes only the
lower
+ // half of the BAR read-only, resulting in a memory BAR request for 4GB.
+ // coreboot does not support BARs of this size, and simnow boot fails.
As
+ // a workaround, limit the BAR read-only check to the lower 32 bits.
This
+ // causes memory BAR requests >= 4GB to be ignored.
+ moving &= 0xFFFFFFFF;
if (moving == 0) {
if (value != 0) {
printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
Thanks,
Scott
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