Hello Kyosti, I do agree with you that it is much easier and straight forward to change memory parameters when you are using the source agesa but it is definitely possible to do this for the binary agesa as well. You can provide the binary AGESA with external tables during run-time.
I do agree with your other points though. Best Regards, Wim Vervoorn Eltan B.V. Ambachtstraat 23 5481 SM Schijndel The Netherlands T : +31-(0)73-594 46 64 E : wvervo...@eltan.com W : http://www.eltan.com "THIS MESSAGE CONTAINS CONFIDENTIAL INFORMATION. UNLESS YOU ARE THE INTENDED RECIPIENT OF THIS MESSAGE, ANY USE OF THIS MESSAGE IS STRICTLY PROHIBITED. IF YOU HAVE RECEIVED THIS MESSAGE IN ERROR, PLEASE IMMEDIATELY NOTIFY THE SENDER BY TELEPHONE +31-(0)73-5944664 OR REPLY EMAIL, AND IMMEDIATELY DELETE THIS MESSAGE AND ALL COPIES." -----Original Message----- From: coreboot [mailto:coreboot-boun...@coreboot.org] On Behalf Of Kyösti Mälkki Sent: Wednesday, May 13, 2015 7:49 AM To: coreboot@coreboot.org Cc: Wolfgang Kamp - datakamp Subject: Re: [coreboot] AGESA PI for Olivehill+ On pe, 2015-05-08 at 09:02 +0000, Wolfgang Kamp - datakamp wrote: > Hello Kyösti, hello Wim, > > with AGESA source there is a file buildOpts.c in the mainboard directory. In > this file you can overwrite seed values and they will be passed to AGESA > build. > With binary Pi this file is absent. How is it possible to pass values to > binary PI? > My AMD support comes from Aschheim-Dornach, Germany. > > Regards, > Wolfgang Wolfgang, with the PI source you are in a better position to develop than any of us in the community contributors. I hope you would push your AMD FAEs to get the API fixed, if you indeed are currently unable to make FT3b work with on-board memory, with the pre-built binaryPI files AMD AES pushes to coreboot 3rdparty / blobs. If you do not do that, You will need to rebase your local changes and rebuild PI part of your firmware image part every time AMD updates their MullinsPI package. I am complaining about the current state of things here as well: http://review.coreboot.org/#/c/9386/ Just beware that what I consider as the official documentation, taken from AMD AES website about PI and coreboot, still states the following in FAQ.462: "Note that the customer MAY NOT ship product with the nonscrubbed PI, as no such rights are provided in the NDA or otherwise. The customer must convert to the IP-scrubbed PI for production." I have tried to have AMD AES to fix/revisit/confirm this statement for 6 months now, since it has not been updated after all the binaryPI invention our partners in crime came up with. I have contacted AMD AES both directly and via their EMEA FAE, but they have pretty much zero response rate nowadays towards coreboot community. Kind Regards, Kyösti Mälkki -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
