Hi Naman, > This finally gave some leads in the qemu debug. There seems be some > misalignment in smp_processor_id. > While tracing in gdb, we have > 0x0000000000000908 in ?? () > => 0x0000000000000908: 06 fe ff 97 bl 0x120 > (which is actually bl smp_processor_id (from src/arch/arm64/stage_entry.S)) > Under arm64_c_environment (in objdump) we have; > 10908: 97fffe06 bl 10120 <loop3_csw+0x1b> > Also in the trace we have > IN: > 0x0000000000000908: 97fffe06 bl #-0x7e8 (addr 0x120) > > Now loop3_csw is defined at (from objdump) > 0000000000010105 <loop3_csw>: > > So this + 0x1b = 10120 > > Thus it wants to branch and link to 0x120 but smp_processor_id is at 121. > > smp_processor_id is at (from objdump) > 0000000000010121 <smp_processor_id>: > > This gives us where the code is failing. Next up is finding out the reason > for this misalignment and rectifying it.
We ran into some code alignment issues with those caching functions recently. This might help: http://crosreview.com/293660 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
