On 11.11.2016 17:12, Patrick Rudolph wrote: > Am Fri, 11 Nov 2016 13:53:16 +0100 > schrieb Nico Huber <[email protected]>: >> On 11.11.2016 08:14, Charlotte Plusplus wrote: >>> I do not know how to adjust the voltage (it should require talking >>> to the IMC of the CPU) but I think that as soon as this is done, >>> stability should improve. >>> >>> If someone can propose a patch doing that (either using the voltage >>> read from SPD, or by manually entering voltage information), I will >>> be happy to test it. >> >> Depending on the board the voltage might not be configurable at all. >> Why should it be if there is only one voltage defined in the standard? >> > The W520 does only have 1.5V DDR voltage. If it's stable with vendor > bios, it's not a DDR voltage problem at all.
That's what I suspected, too. >>> >>> For now, I urge caution when operating even at DDR-1866 >>> frequencies. Most boards do set up 933 as their max_mem_clock_mhz. >>> It is not very prudent to do that until the voltage situation can >>> be solved. >> >> If the board can work at that frequency, that's just fine. If the >> voltage is a problem, it's due to the memory module. IMHO, the rule >> should be to ignore SPD frequency settings that include an out of spec >> voltage. > That's what sandybridge raminit does. Only XMP profiles with DDR > voltage of 1.5V are used. Profiles that do have other voltage > setting are ignored. Good to know, I already started worrying about your code just by reading emails. Should have looked in the code instead ;) my apologies. Nico -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
