Hello Zheng, For decades, I've been FW/SW engineer, but I do understand a little bit of a HW. I have looked into the Si52111-B5 data sheet for clarification.
My problem here is to understand, your use case: do you use local xtal attached to Si52111-B5 to generate local PCIe 25MHz clock? If you do this, my next question is how you synchronize these two clocks: Local PCIe 25 MHz and common reference clock from CPU? Since these two clocks, as I understand above scenario, are asynchronous to each other?! Please, clarify for us your use case. Thank you, Zoran _______ On 1/12/17, Zheng Bao <[email protected]> wrote: > Our VPX design uses separate reference clock source, which is Si52111-B5 (No > spread), instead of common ref clock from CPU. > Now The system is unstable. Reading PCIE configuration space is unstable > too. (If we add some fly wire to make it work with common ref clock, the > system becomes stable.) > > (abstracted from PCIe spec: 12 Slot Clock Configuration - This bit indicates > that the > component uses the same physical reference clock that the > platform provides on the connector. If the device uses an > independent clock irrespective of the presence of a reference > clock on the connector, this bit must be clear. > For a multi-Function device, each Function must report the > same value for this bit.) > > Based on my understanding, the BIOS need to read bit "Slot Clock > Configurationclear" to see if > separate ref clock is used. BIOS then write bit "Common Clock > Configuration". > > On our board, the bit "Slot Clock Configuration" is always 1, which I assume > should be 0. > > My question is, how the hardware affect the bit "Slot Clock Configuration"? > How do we need to design our board to make the bit "Slot Clock > Configuration" be 0? > > Thanks. > > Zheng > > -- coreboot mailing list: [email protected] https://www.coreboot.org/mailman/listinfo/coreboot
