> As for our prototype, we got it to boot with one memory channel while ‘hot’. We’re working with Intel to narrow it down, > but it looks like a marginal trace length issue. The verbose FSP tells us we are having issues during Command Clock Training.
As I recall, INTEL provides HW PCB evaluation support for custom platforms, for VIP IOTG customers. There is also INTEL trace length calculation tool, for each family of ATOM/CORE. Important things to note (area: board HW design and verification), Andy. [image: Inline image 1] Since I also recall that Rangeley has some Gen.3 SATA support (2 ports), I also will advise you to check/pay attention to these, during Lane Clock training/SATA 3 Protocol training... Just in case. Good Luck, Zoran On Thu, Feb 2, 2017 at 2:28 PM, Andy Knowles <[email protected]> wrote: > A follow-up, for posterity: > > > > I got the RCC-DFF from ADI to boot using the memory down option. To do > this, I enabled Memory Down in the FSP (via BCT) and also changed all of > the SPD SMBus Addresses to 0xff, to make sure the EEPROM wasn’t being > used. Booting with this FSP I get an expected “No DIMMs Present” error. > > > > I then modified src/mainboard/adi/rcc-dff/romstage.c as attached, > specifying the SPD data from the Kingston datasheet and one populated DIMM > on channel 0. > > > > The RCC-DFF then booted normally. > > > > As for our prototype, we got it to boot with one memory channel while > ‘hot’. We’re working with Intel to narrow it down, but it looks like a > marginal trace length issue. The verbose FSP tells us we are having issues > during Command Clock Training. > > > > Thanks again for responses! > > > > Andy > > > > > > *From:* coreboot [mailto:[email protected]] *On Behalf Of *Andy > Knowles > *Sent:* Monday, 23 January 2017 11:55 > *To:* Agrain Patrick <[email protected]> > *Cc:* [email protected] > *Subject:* Re: [coreboot] Rangeley FSP reports "Err[24]: GetSet Value > exceeds limits" during memory init > > > > This sender failed our fraud detection checks and may not > be who they appear to be. Learn about spoofing > <http://aka.ms/LearnAboutSpoofing> > > Feedback <http://aka.ms/SafetyTipsFeedback> > > Hi Patrick, > > > > I have an RCC-DFF from ADI. The memory is soldered down, but from their > BIOS source it seems they aren’t using the FSP memory down option, so I > suspect they have an EEPROM on the board with SPD data pretending to be a > DIMM. I’m going to try booting it with memory down set in FSP and SPD data > in coreboot instead. > > > > Thanks, > > Andy > > > > *From:* Agrain Patrick [mailto:[email protected] > <[email protected]>] > > HI Andy, > > > > RCC-VE dev board from ADI has also memory down. It may help to compare. > But unfortunately, schematics are not available. > > Regards, > > Patrick Agrain > > > > -- > coreboot mailing list: [email protected] > https://www.coreboot.org/mailman/listinfo/coreboot >
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