On 2017-03-12 18:58, Kyösti Mälkki wrote:
As indicated by the clean boot log, it's a failure to write MRC cache. Could be that our SPI flash routines have regressed or were never tested for a setup with 4Mib + 8MiB SPI flash parts installed. Or there may be some unwritten rule about CBFS size and the location of MRC cache.
I see. Is there anything I can do to help? Gert -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot
