Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.
6 new defect(s) introduced to coreboot found with Coverity Scan. 5 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 6 of 6 defect(s) ** CID 1375445: Uninitialized variables (UNINIT) /src/soc/rockchip/rk3399/mipi.c: 159 in rk_mipi_dsi_phy_init() ________________________________________________________________________________________________________ *** CID 1375445: Uninitialized variables (UNINIT) /src/soc/rockchip/rk3399/mipi.c: 159 in rk_mipi_dsi_phy_init() 153 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 154 SETRD_MAX | POWER_MANAGE | 155 TER_RESISTORS_ON); 156 157 write32(&mipi_regs->dsi_phy_rstz, PHY_ENFORCEPLL | PHY_ENABLECLK | 158 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); >>> CID 1375445: Uninitialized variables (UNINIT) >>> Using uninitialized value "ret". 159 return ret; 160 } 161 162 static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) 163 { 164 switch (fmt) { ** CID 1375444: Integer handling issues (REVERSE_NEGATIVE) /src/soc/intel/common/block/i2c/i2c.c: 101 in lpss_i2c_dev_init() ________________________________________________________________________________________________________ *** CID 1375444: Integer handling issues (REVERSE_NEGATIVE) /src/soc/intel/common/block/i2c/i2c.c: 101 in lpss_i2c_dev_init() 95 { 96 const struct lpss_i2c_bus_config *config; 97 int bus = lpss_i2c_dev_to_bus(dev); 98 99 config = i2c_get_soc_cfg(bus, dev); 100 >>> CID 1375444: Integer handling issues (REVERSE_NEGATIVE) >>> You might be using variable "bus" before verifying that it is >= 0. 101 if (!config || bus < 0) 102 return; 103 104 lpss_i2c_init(bus, config); 105 } 106 ** CID 1375443: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/rockchip/rk3399/mipi.c: 194 in rk_mipi_dsi_get_lane_bps() ________________________________________________________________________________________________________ *** CID 1375443: Integer handling issues (OVERFLOW_BEFORE_WIDEN) /src/soc/rockchip/rk3399/mipi.c: 194 in rk_mipi_dsi_get_lane_bps() 188 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 189 if (bpp < 0) { 190 printk(BIOS_DEBUG, "failed to get bpp for pixel format %d\n", 191 dsi->format); 192 return bpp; 193 } >>> CID 1375443: Integer handling issues (OVERFLOW_BEFORE_WIDEN) >>> Potentially overflowing expression "edid->mode.pixel_clock * 1000U" >>> with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit >>> arithmetic, and then used in a context that expects an expression of type >>> "u64" (64 bits, unsigned). 194 pclk = edid->mode.pixel_clock * MSECS_PER_SEC; 195 /* take 1 / 0.8, since mbps must bigger than bandwidth of RGB */ 196 target_bps = pclk / dsi->lanes * bpp / 8 * 10; 197 if (target_bps >= max_bps) { 198 printk(BIOS_DEBUG, "DPHY clock frequency is out of range\n"); 199 return -1; ** CID 1375442: Control flow issues (NO_EFFECT) /src/soc/intel/apollolake/i2c.c: 47 in i2c_soc_bus_to_devfn() ________________________________________________________________________________________________________ *** CID 1375442: Control flow issues (NO_EFFECT) /src/soc/intel/apollolake/i2c.c: 47 in i2c_soc_bus_to_devfn() 41 return PRERAM_I2C_BASE_ADDRESS(bus); 42 } 43 44 /* Convert I2C bus number to PCI device and function */ 45 int i2c_soc_bus_to_devfn(unsigned int bus) 46 { >>> CID 1375442: Control flow issues (NO_EFFECT) >>> This greater-than-or-equal-to-zero comparison of an unsigned value is >>> always true. "bus >= 0U". 47 if (bus >= 0 && bus <= 3) 48 return PCI_DEVFN(PCH_DEV_SLOT_SIO1, bus); 49 else if (bus >= 4 && bus <= 7) 50 return PCI_DEVFN(PCH_DEV_SLOT_SIO2, (bus - 4)); 51 else 52 return -1; ** CID 1375441: Integer handling issues (NEGATIVE_RETURNS) /src/soc/intel/common/block/i2c/i2c.c: 122 in lpss_i2c_acpi_fill_ssdt() ________________________________________________________________________________________________________ *** CID 1375441: Integer handling issues (NEGATIVE_RETURNS) /src/soc/intel/common/block/i2c/i2c.c: 122 in lpss_i2c_acpi_fill_ssdt() 116 enum i2c_speed speeds[LPSS_I2C_SPEED_CONFIG_COUNT] = { 117 I2C_SPEED_STANDARD, 118 I2C_SPEED_FAST, 119 I2C_SPEED_FAST_PLUS, 120 I2C_SPEED_HIGH, 121 }; >>> CID 1375441: Integer handling issues (NEGATIVE_RETURNS) >>> Assigning: signed variable "bus" = "lpss_i2c_dev_to_bus". 122 int i, bus = lpss_i2c_dev_to_bus(dev); 123 124 bcfg = i2c_get_soc_cfg(bus, dev); 125 126 if (!bcfg) 127 return; ** CID 1375440: Integer handling issues (NEGATIVE_RETURNS) /src/soc/intel/common/block/i2c/i2c.c: 97 in lpss_i2c_dev_init() ________________________________________________________________________________________________________ *** CID 1375440: Integer handling issues (NEGATIVE_RETURNS) /src/soc/intel/common/block/i2c/i2c.c: 97 in lpss_i2c_dev_init() 91 * The device should already be enabled and out of reset, 92 * either from early init in coreboot or SiliconInit in FSP. 93 */ 94 static void lpss_i2c_dev_init(struct device *dev) 95 { 96 const struct lpss_i2c_bus_config *config; >>> CID 1375440: Integer handling issues (NEGATIVE_RETURNS) >>> Assigning: signed variable "bus" = "lpss_i2c_dev_to_bus". 97 int bus = lpss_i2c_dev_to_bus(dev); 98 99 config = i2c_get_soc_cfg(bus, dev); 100 101 if (!config || bus < 0) 102 return; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbLuoVetFLSjdonCi1EjfHRqWGQvojmmkYaBE-2BPJiTQvQ-3D-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5ZoLnM8Wul9CLIe2r7u7QI8lkUPVCJnjLgxhZ2Vv5HdtIcXWu5qkf7ehkqu3DaB0dhE4q9lyzDMaWISMuL2ctHyeO10FwmdqgkACIvtmuaiF6rgljUiV3SxE1laRJPm3G-2BNkZITYyLWr2GAxlYxrxnxfij-2FWr62moqX-2BOsCI17DXc7l2sSaRcikTVuB-2FI1ZtZs-3D To manage Coverity Scan email notifications for "coreboot@coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V05UPxvVjWch-2Bd2MGckcRbVDbis712qZDP-2FA8y06Nq4e-2BpBzwOa5gzBZa9dWpDbzfofODnVj1enK2UkK0-2BgCCqyeem8IVKvTxSaOFkteZFcnohwvb2rnYNjswGryEWCURnUk6WHU42sbOmtOjD-2Bx5c-3D_q4bX76XMySz3BXBlWr5fXXJ4cvAsgEXEqC7dBPM7O5ZoLnM8Wul9CLIe2r7u7QI8HiVgDp2Qkf27t3vt2Ak9-2Bjosq-2B1XQASUZKv28y7u0dvdfTHEz-2BGr11IXAQAKEctucYgrtQYUQqdFnlrS6Efc57nGWAbXxefvJmRsdAR5mHFzbcvi7aA0FGxyW-2BI6z3Yjsupx8JoXc-2F0Ed4E4LRCZMkbQ9BGhlQ9kw8HRQlWeX5Q-3D -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot