On 04.07.2017 14:05, Martin Kepplinger wrote: > So you are talking about external SPI flashing. There are 2 flash chips and > the gbe part is in the "second", 8MB one, > > For the bios (coreboot with payload), you only need to access the "first", 4MB > chip,
Please don't name the chips in that order. They are concatenated as one 12MiB part where the 8MiB is the lower (first) part and the 4MiB the upper (second) part. Nico -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
