On 11/02/2017 01:36 AM, [email protected] wrote:
> On 11/01/2017 08:06 AM, Lucian Cojocar wrote:
> 
>> Hi,
>>
>> Is coreboot working on the H8SGL-F motherboard[1] with AMD Opteron 6168
>> (10h Family)?
> Probably not, the code hasn't been modified since 2011.
> 
> I would just get a KGPE-D16, then you can use OpenBMC (it is very nice
> to have) and benefit from the coreboot fam15h native init code that has
> IOMMU for 62xx and 63xx CPU's.
>> I know there is support for the H8SCM-F[2] board, which is very similar.
>> The only difference between the two boards seems to be the socket. It
>> seems there was some interest in this direction a while back ago[3].
> G34 vs C32 is potato potatoe (same thing)
> If you want quad socket you could probably port either board to the
> native init code without much effort if you know what you are doing then
> gain IOMMU support (that AGESA has no IOMMU support, it will also be
> removed from coreboot soon due to some silly choices by the leadership
> meaning you wouldn't be able to use these boards on the future released
> versions even if they did work)

What is the impact of having no IOMMU support? Is it just that most of
the devices won't work? Or is it that I won't be able to access (and
run) from the main DRAM?

My goal is to run some memory reliability tests with (a modified)
memtest. In terms of IO, it would be enough if I get the serial working
after coreboot+payload and also if I can access the DRAM controller (via
some PCI addresses). I'm mostly interested in playing with the part of
coreboot (actually AGESA) that does the initialization of the memory
controller. For these tests I only need one core.

An extra feature would be to be able to revert to old BIOS -- for this I
plan to re-program the flash with its initial contents by using some
soldering/clips. Is there a easier way? e.g. can I do it from my
/hopefully somewhat functional/ coreboot?

Thanks,
Lucian

Attachment: signature.asc
Description: OpenPGP digital signature

-- 
coreboot mailing list: [email protected]
https://mail.coreboot.org/mailman/listinfo/coreboot

Reply via email to