Hello Hilbert,

I am currently at job, so I do not have any time to look into it/into
your maximal log, enabled now. Somebody from Google folks assigned to
Coreboot might want to chime in. :-)

I will look to your log later tonite.

Thank you,
Zoran

On Wed, Jan 3, 2018 at 9:56 AM, Hilbert Tu(杜睿哲_Pegatron)
<hilbert...@pegatroncorp.com> wrote:
> Hi Zoran,
>
> I have changed to maximal log level and found SMBus init was failed when 
> enabling clock gating. Do you have any comments about this? Thanks.
>
> -Hilbert
>
> -----Original Message-----
> From: Hilbert Tu(杜睿哲_Pegatron)
> Sent: Tuesday, January 02, 2018 9:41 AM
> To: 'Zoran Stojsavljevic'
> Cc: David Hendricks; coreboot@coreboot.org
> Subject: Re: [coreboot] BDX-DE PCI init fail
>
> Hi Zoran,
>
> The log was just at following link:
> http://mail.coreboot.org/pipermail/coreboot/attachments/20171227/b07eb74e/attachment.txt
> With messages:
>
>         MTRR check
>         Fixed MTRRs   : Enabled
>         Variable MTRRs: Enabled
>
> By the way, I have tried to use U-Boot and Grub2 as payload, but I don't 
> think the payload was executed since it failed at PCI 00:1f.3 init.
>
> -Hilbert
>
> -----Original Message-----
> From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
> Sent: Saturday, December 30, 2017 2:32 PM
> To: Hilbert Tu(杜睿哲_Pegatron)
> Cc: David Hendricks; coreboot@coreboot.org
> Subject: Re: [coreboot] BDX-DE PCI init fail
>
>> I still have same issue even tried to comment out the 1f.3 device in
>> ./src/mainboard/intel/camel- backmountain_fsp/devicetree.cb then
>> rebuild coreboot.
>
> You wrote that you submitted the log. Is this the full log? I doubt. I do NOT 
> see physical memory layout as well as MTRR layout.
>
> Could you, please, submit the full/complete log?
>
> Which payload are you using? SeaBIOS?
>
> Thank you,
> Zoran
>
> On Fri, Dec 29, 2017 at 5:58 AM, Hilbert Tu(杜睿哲_Pegatron)
> <hilbert...@pegatroncorp.com> wrote:
>> Hi David,
>>
>>
>>
>> Thanks for your information.
>>
>> I still have same issue even tried to comment out the 1f.3 device in
>> ./src/mainboard/intel/camelbackmountain_fsp/devicetree.cb then rebuild
>> coreboot.
>>
>> Could you let me know how to do that?
>>
>>
>>
>> -Hilbert
>>
>>
>>
>> From: David Hendricks [mailto:david.hendri...@gmail.com]
>> Sent: Friday, December 29, 2017 9:46 AM
>> To: Hilbert Tu(杜睿哲_Pegatron)
>> Cc: coreboot@coreboot.org
>> Subject: Re: [coreboot] BDX-DE PCI init fail
>>
>>
>>
>> Hi Hilbert,
>>
>> Have you had any luck? I have a board with a similar problem.
>> Commenting out the entry for device 1f.3 in devicetree.cb seemed to
>> help (I copied src/mainboard/intel/camelbackmountain_fsp for my project).
>>
>>
>>
>> On Wed, Dec 27, 2017 at 2:17 AM, Hilbert Tu(杜睿哲_Pegatron)
>> <hilbert...@pegatroncorp.com> wrote:
>>
>> Hi,
>>
>>
>>
>> I am porting coreboot on Intel BDX-DE platform and it gets stuck when
>> init PCI 00:1f.3. This device should be SMBus, serial management bus.
>> But I don’t know why this happened. Does anyone can give me some hint?
>> Attached is my boot up log. Thanks in advance.
>>
>>
>>
>> -Hilbert
>>
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