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On 03/22/2018 10:27 AM, Daniel Wagner wrote: > Hi Piotr, Hi Daniel, (...) > > Is the TXE code also part of the rom? I wonder why it is not > showing up in the ifdtool output. It shows under position of ME. ME for Bay Trail is called TXE. (...) >> This will give you layout file similar to: 00000000:00000fff fd >> 00400000:007fffff bios 00001000:003fffff me 00000000:00000fff >> gbe > I got this as well. Zoran just told me offline that fd and gbe > seems to overlap. He also told me that the layout should be fd, > gbe, me and finally bios. Is the ifdtool output correct? I also wonder about that. IMO there can be 2 things - incorrect parsing of flash descriptor by ifdtool or incorrect values in flash descriptor. This may be because this firmware doesn't have GbE firmware. I wondered what will happen if we apply different permissions to fd and gbe. If you look at addresses bios is at the end. At least this layout works. How to interpret overlapping regions I don't know. > >> Then copy build/coreboot.rom and layout file to your RPi and >> flash: >> >> (rpi) $ flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=32000 >> -l \ layout -i bios -w /tmp/coreboot.rom >> >> Our container have default FSP from GitHub which is not the most >> recent one. Latest you can obtain only through Intel RDC portal. > > I suppose the one from GitHub is good enough though? I don't have > an RDC portal account. Yes. But if you would like to complain to Intel for performance related stuff they will say "please use recent one" and then you can complain on correct one :) Best Regards, - -- Piotr Król Embedded Systems Consultant http://3mdeb.com | @3mdeb_com -----BEGIN PGP SIGNATURE----- iQIzBAEBCgAdFiEE4DCbLYWmfoRjKeNLsu5x6WeqnkwFAlqz1fkACgkQsu5x6Weq nkwM2w//cpHjQEwx/DcLLOY4cmApO99LyP6IgiclrfufXHAavrbDjAhjcq/hz93i Ol5cJ04nPcMcwqfXJLOMax7ZQnihjqeRN9lKTyICGDhs6DxNPPjk0Q8A3+3A2chd tjklNoP5NOd9DQbMoPSJ4CrvO2r+DcJY8myWgO8qVhCtj5ONLH9o/xpLb/4YHIXe Iah2SuMt3ExPkWZ245ksiLzzV7eVaLHoIv7jbwz8vN1vHXAeTHjlDcZAZ0qLpHE8 Ggd/mvlZCCkal8hR9CiW+ZS8l/S+Zd0++veMOAcU3VKowRCmmWmP76dhGytK/nBw xZByMT0eAUDWg4JtizCmELz8x14IgihyeotRumczix/mKotKlZUgOJeje3Vhxzwt nRkN7ShSRM96CPh9JPiiFGPUhbQKvRcbSflnQa7pkcSMYDBkokToRmWKsJQPH2Z2 KISrTWaBR4GkkcsWh2DRVjcgCOPEFeYcowU55/t5y4oBBYGs1j4SNQrtLTD0VIT0 NCinhHDs8DEP21FB+QPUhdCRHjYpkYsr1Wf1FVYf2ZDW72+h+w1y97gfbraZta6g ISAjS7gSj8b9OJpjROpjiJjnyhKn+u8syxlMBcl/nyqjwx4w+MY7D+Rzizi4ldEl epoHQl7jp90I3l/RgeCRp3pXpFHSsGxi7Ujv/Sv4VRTIAeX3AsU= =DurI -----END PGP SIGNATURE----- -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot