I suggest you better check
1. power on sequence,
2. every power/ voltage rail stability during boot process.
3. Over/undershoot.
4. all crystal osc frequency stability during boot process.

5. Try to print the DID early during bootblock and romstage.

Provide your observations.

Regards,
Naresh G Solanki
-- 
coreboot mailing list: [email protected]
https://mail.coreboot.org/mailman/listinfo/coreboot

Reply via email to