Hi Nico, I did not do any code changes in coreboot. The messages are coming from a debug version of FSP I got from Intel. I did not patch this fsp.fd at all.
I expected that this version will help me to patch my FSP using BCT. Can you tell how to use the above FSP messages to patch FSP ? For example: what are RID , Reg_EFF_DualCH_EN ? Attached the output of dmidecode and decode-dimms I ran on this board under ubuntu. Hope I can attach files here. Thank you, Zvika On Tue, Feb 12, 2019 at 8:35 PM Nico Huber <[email protected]> wrote: > Hi Zvika, > > On 09.02.19 20:40, Zvi Vered wrote: > > PcdMrcInitSPDAddr1 = A0 > > PcdMrcInitSPDAddr2 = A2 > > ... > > C0.D0: SPD not present. > > C1.D0: SPD not present. > > Did you solve this SPD problem yet? If not, this is likely still where > your later logs end, i.e. in FSP's raminit. It seems you try to tell FSP > to read them from the SMBus addresses above. If the addresses are cor- > rect and the SPD chips present, it might not find them because the SMBus > is not functional. IIRC, you have to configure the SoC pads explicitly > to be used for SMBus. This is the first thing I'd investigate. > > If you could push your code to Gerrit, or any public Git repository, we > might be able to help you better. > > Nico >
dmidecode.log
Description: Binary data
decode-dimms.log
Description: Binary data
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