On Wed, Oct 9, 2019 at 3:07 PM Jeremy Soller <jer...@system76.com> wrote:
> Will do. Any relevant emails I should CC when I have something? > I'm not sure about Intel, but you can include mine, Duncan's, and Furquan's. Should be autocomplete in gerrit. > > -- > Jeremy Soller > System76 > Engineering Manager > jer...@system76.com > > > > On Wed, Oct 9, 2019, at 1:29 PM, Aaron Durbin wrote: > > Please include intel and google on your patches because we'll be needing > this support in the near future as well. The allocator limitations are > known, and Kyosti and I have talked about improving things here. As for the > children comment you need to reserve a sufficiently large mmio space and in > the hotplug path one can allocate subdevices. Since it's inherently a > hotplug there's no way to know what the topology will be when a device is > plugged in. > > On Wed, Oct 9, 2019 at 12:32 PM Jeremy Soller <jer...@system76.com> wrote: > > This is to continue the discussion from the coreboot leadership meeting. > Thunderbolt devices are not correctly initialized by Coreboot such that the > OS can boot without kernel parameters and allow for Thunderbolt > hotplugging. Additional bus numbers and memory must be allocated. > > I will be working on support for this for our System76 mainboards. > > Here were the notes taken about it during the meeting, see 9 October 2019, > PCIe Hotplug on newer Intel socs: > > > https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit#heading=h.pcmhez7yc2on > > -- > Jeremy Soller > System76 > Engineering Manager > jer...@system76.com > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org > > >
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