> > System *boots* with one of: > > 1. maxcpus=0 (equivalent nosmp) > 2. maxcpus=1 > 3. nolapic (with e1000 warning about missing MSI-X > > System does *not* boot with one of: > > 1. maxcpus=2 > 2. noapic >
I thought SMP was generally not compatible with PIC IRQ routing (which noapic enforces?) and this would explain case 2. As for case 1, maybe I missed some detail with my commit [1] when switching from LAPIC to TSC timers. Like leaving LAPIC timers running at different rate or generally having the timer counters too much out-of-sync across CPU #0 and #1. You coud try if that one is the commit with regression. [1] https://review.coreboot.org/c/coreboot/+/34200 Kyösti _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
