UPDATE: fam15tn A88XM-E is booting well if all 3 fixes applied together with this patch above (separately not enough to get it working) - tested it enough. However, when I tried a similar fix for fam16kb AM1I-A - it got stuck in a boot loop (see the attached log). Maybe I'm doing something wrong and it worked for fam15tn just by a coincidence. Please take a look at change for a further review https://review.coreboot.org/c/coreboot/+/41431
On Fri, May 15, 2020 at 1:30 PM Mike Banon <mikeb...@gmail.com> wrote: > > Looking at your change 41369 - soc/amd/stoneyridge: add resources > during read_resources() - I tried to do a similar style change on top > of your 3 fixes above, and surprisingly it worked at first try - now > I'm able to see the boot devices and floppies. New bootlog is > attached. After testing it more (should be able to boot 100% of times) > I'm going to submit it to review coreboot org soon, for your review - > and also we will need to do a similar change for family14 and > family16kb if this one succeeds. > > diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c > b/src/northbridge/amd/agesa/family15tn/northbridge.c > index 9d41e7a1f1..0194ea82ea 100644 > --- a/src/northbridge/amd/agesa/family15tn/northbridge.c > +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c > @@ -666,6 +666,8 @@ static void domain_set_resources(struct device *dev) > u32 reset_memhole = 1; > #endif > > + domain_read_resources(dev); > + > pci_tolm = 0xffffffffUL; > for (link = dev->link_list; link; link = link->next) { > pci_tolm = find_pci_tolm(link); > @@ -749,17 +751,18 @@ static void domain_set_resources(struct device *dev) > } > > add_uma_resource_below_tolm(dev, 7); > - > +/* > for (link = dev->link_list; link; link = link->next) { > if (link->children) { > assign_resources(link); > } > } > +*/ > } > > static struct device_operations pci_domain_ops = { > - .read_resources = domain_read_resources, > - .set_resources = domain_set_resources, > + .read_resources = domain_set_resources, > + .set_resources = pci_domain_set_resources, > .scan_bus = pci_domain_scan_bus, > }; > > > On Fri, May 15, 2020 at 12:10 PM Mike Banon <mikeb...@gmail.com> wrote: > > > > Although it's still the same result even with three changes (either > > can't boot or no boot devices, randomly) - there is a positive effect > > that USB FT232H log now 't stop and I'm finally able to share a full > > log for a boot problem. Please compare these two logs: > > 1) ok_e6fb1344ed9188e19be4b54bdf1a76680b8c4523.txt - boot log for last > > "working" commit (before the allocator changes) > > 2) 3fixes.txt - boot log with 3 changes applied on top of > > 6b95507ec5b087658178a325bdc68570bc48bb20 (after the allocator changes) > > Hope this comparison will give enough clues about how to fix it > > further - and I'll happily test your new changes aimed on fixing this > > > > Best regards, > > Mike Banon > > > > On Fri, May 15, 2020 at 2:44 AM Furquan Shaikh > > <furquan.m.sha...@gmail.com> wrote: > > > > > > I have uploaded 2 changes on top of Aaron's change. Can you please > > > give these three changes a try: > > > https://review.coreboot.org/c/coreboot/+/41363 > > > https://review.coreboot.org/c/coreboot/+/41418 > > > https://review.coreboot.org/c/coreboot/+/41419 > > > > > > Thank you! > > > > > > - Furquan > > > > > > On Thu, May 14, 2020 at 4:16 PM Aaron Durbin <adur...@google.com> wrote: > > > > > > > > > > > > > > > > On Thu, May 14, 2020 at 3:46 PM Aaron Durbin <adur...@google.com> wrote: > > > >> > > > >> > > > >> > > > >> On Thu, May 14, 2020 at 2:46 PM Mike Banon <mikeb...@gmail.com> wrote: > > > >>> > > > >>> Unfortunately it seems a lot of boards are affected by this. A88XM-E > > > >>> and Lenovo G505S (AMD fam15h) also got broken: they rarely succeed at > > > >>> booting - and, when they do, no boot devices are available (virtual > > > >>> floppies too, for some reason) - except coreinfo/tint secondary > > > >>> payloads which became prone to freezing. I attach the A88XM-E logs > > > >>> I've been able to obtain with USB FT232H: > > > >>> > > > >>> 1) ok_e6fb1344ed9188e19be4b54bdf1a76680b8c4523.txt - last coreboot > > > >>> repo's revision where all the stuff works > > > >>> 2) fail_1_3b02006afe8a85477dafa1bd149f1f0dba02afc7.txt - this commit > > > >>> got the boards broken for the first time > > > >>> 3) fail_2_6b95507ec5b087658178a325bdc68570bc48bb20.txt - this is a log > > > >>> for coreboot's master top > > > >>> > > > >>> For some reason logs for 2) and 3) always stop after "PCI: 00:12.2 > > > >>> EHCI Debug Port hook triggered". > > > >>> > > > >>> I hope these commits could be reverted before we figure out what's > > > >>> going on with them. Good thing we've noticed it fast enough. > > > >>> > > > >> > > > >> Thanks, Mike. The amd chipset code (all of it from what I can tell) is > > > >> fundamentally broken and at odds with all of the resource allocation > > > >> flow. They worked previously because dynamic resources were being > > > >> assigned using an algorithm that just assumed there weren't > > > >> collisions, and that was done w/o all the necessary info required for > > > >> making the proper decisions regarding dynamic resource allocation. > > > >> > > > >> I landed the other chipsets' fixes, but the amd chipset code is going > > > >> to take a lot more to fix. Would you be willing to test patches as > > > >> they are crafted? Given the largeness of the problem as well as the > > > >> gnarly code that is the amd chipset code it's going to take some time > > > >> so I think we do need to revert the allocator changes until we can do > > > >> some house keeping. > > > >> > > > > > > > > I just was brainstorming with Furquan. He did push the revert changes, > > > > but we were scheming on a patch that I was hoping affected parties > > > > could try in conjunction with > > > > https://review.coreboot.org/c/coreboot/+/41363. Basically we'll > > > > allocate top down like the previous allocator did hoping for no > > > > collisions. Let's try that, and see where we land. Regardless we need > > > > to fix this amd chipset code as it's a major liability. > > > >> > > > >> -Aaron > > > >>> > > > >>> Best regards, > > > >>> Mike Banon > > > >>> > > > >>> On Thu, May 14, 2020 at 8:47 PM Keith Hui <buu...@gmail.com> wrote: > > > >>> > > > > >>> > Hi guys, > > > >>> > > > > >>> > 31ab7de51a is CB:41368, cherry picked into my local repo. > > > >>> > > > > >>> > Turns out I have to back out all four of Furquan's patches > > > >>> > (CB:39486~39489) for my board to boot normally again. > > > >>> > > > > >>> > Thoughts? > > > >>> > > > > >>> > I'll now get a log with everything in at SPEW. > > > >>> > > > > >>> > > > > >>> > On Thu, May 14, 2020 at 1:05 PM Aaron Durbin <adur...@google.com> > > > >>> > wrote: > > > >>> > > > > > >>> > > Keith, is it possible to have the console log level set to SPEW? > > > >>> > > I'm not seeing the full logs to piece it all together. > > > >>> > > > > > >>> > > Allocating resources... > > > >>> > > Reading resources... > > > >>> > > Setting RAM size to 768 MB > > > >>> > > PNP: 03f0.8 missing read_resources > > > >>> > > Done reading resources. > > > >>> > > Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) > > > >>> > > Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) > > > >>> > > Resource ranges: > > > >>> > > Base: 1000, Size: d000, Tag: 100 > > > >>> > > Base: f000, Size: 1000, Tag: 100 > > > >>> > > Resource ranges: > > > >>> > > Base: 0, Size: ff800000, Tag: 200 > > > >>> > > Base: 100000000, Size: f00000000, Tag: 100200 > > > >>> > > Resource ranges: > > > >>> > > Base: 10000000, Size: 8000000, Tag: 1200 > > > >>> > > Resource ranges: > > > >>> > > Base: 18000000, Size: 1100000, Tag: 200 > > > >>> > > > > > >>> > > This is the memory address space: > > > >>> > > Base: 0, Size: ff800000, Tag: 200 > > > >>> > > Base: 100000000, Size: f00000000, Tag: 100200 > > > >>> > > > > > >>> > > Those are valid ranges to choose dynamic resources from. > > > >>> > > > > > >>> > > PCI: 00:00.0 10 <- [0x0000000000 - 0x000fffffff] size 0x10000000 > > > >>> > > gran 0x1c prefmem > > > >>> > > > > > >>> > > I see 'Setting RAM size to 768 MB' which means I would expect to > > > >>> > > see a hole in the ranges representing 768MiB. > > > >>> > > > > > >>> > > that would be bad. I don't know what commit '31ab7de51a' is, but > > > >>> > > it might not contain the CB:41368. Having SPEW logs would be > > > >>> > > helpful. > > > >>> > > > > > >>> > > Also, what mainboard Kconfig are you selecting for p3bf? > > > >>> > > src/mainboard/asus/p2b ? > > > >>> > > > > > >>> > > > > > >>> > > > > > >>> > > On Thu, May 14, 2020 at 10:42 AM Keith Hui <buu...@gmail.com> > > > >>> > > wrote: > > > >>> > >> > > > >>> > >> (Temporarily leaving the list out) > > > >>> > >> > > > >>> > >> Hi Aaron, > > > >>> > >> > > > >>> > >> Here is a log with everything including CB:41368 included. I'll > > > >>> > >> get > > > >>> > >> this log out to you first, while I try a build with all problem > > > >>> > >> commits left out. > > > >>> > >> > > > >>> > >> Thanks > > > >>> > >> Keith > > > >>> > >> > > > >>> > >> On Thu, May 14, 2020 at 12:53 AM Aaron Durbin > > > >>> > >> <adur...@google.com> wrote: > > > >>> > >> > > > > >>> > >> > > > > >>> > >> > > > > >>> > >> > On Wed, May 13, 2020 at 10:51 PM Keith Hui <buu...@gmail.com> > > > >>> > >> > wrote: > > > >>> > >> >> > > > >>> > >> >> Hi guys, > > > >>> > >> >> > > > >>> > >> >> I tested these fixes on my board, and I have to say there's > > > >>> > >> >> still > > > >>> > >> >> something wrong. They did address the hang or reset in > > > >>> > >> >> SeaBIOS I first > > > >>> > >> >> described, but now either my ATA hard drive failed to boot > > > >>> > >> >> (it tried > > > >>> > >> >> to hand off to GRUB on my drive, but didn't get there), or it > > > >>> > >> >> can't > > > >>> > >> >> find the option ROM of my video card, meaning no display. > > > >>> > >> >> > > > >>> > >> >> Now I want to try the other way, testing a build with all > > > >>> > >> >> changes > > > >>> > >> >> related to the problem backed out instead. So besides the one > > > >>> > >> >> I first > > > >>> > >> >> identified, what other related patches should I try backing > > > >>> > >> >> out? > > > >>> > >> > > > > >>> > >> > > > > >>> > >> > Just go to the parent of the identified patch. As for the > > > >>> > >> > other symptoms you are seeing, I'd love to see logs with the > > > >>> > >> > patches we identified so we can root cause. > > > >>> > >> > > > > >>> > >> > Thanks. > > > >>> > >> > > > > >>> > >> > -Aaron > > > >>> > >> > > > > >>> > >> >> > > > >>> > >> >> On Wed, May 13, 2020 at 11:54 PM Furquan Shaikh > > > >>> > >> >> <furquan.m.sha...@gmail.com> wrote: > > > >>> > >> >> > > > > >>> > >> >> > Similar fix for i440x: > > > >>> > >> >> > https://review.coreboot.org/c/coreboot/+/41368 > > > >>> > >> >> > > > > >>> > >> >> > On Wed, May 13, 2020 at 11:29 AM Aaron Durbin > > > >>> > >> >> > <adur...@google.com> wrote: > > > >>> > >> >> > > > > > >>> > >> >> > > i440x chipset is doing things in the wrong way like > > > >>> > >> >> > > sandybridge. I uploaded this fix for sandy: > > > >>> > >> >> > > https://review.coreboot.org/c/coreboot/+/41364 We'll need > > > >>> > >> >> > > to do the equivalent for i440x. > > > >>> > >> >> > > > > > >>> > >> >> > > On Wed, May 13, 2020 at 11:13 AM Aaron Durbin > > > >>> > >> >> > > <adur...@google.com> wrote: > > > >>> > >> >> > >> > > > >>> > >> >> > >> OK. I'll take a look at your logs and see what's going > > > >>> > >> >> > >> on. The patch link I sent was based off of someone > > > >>> > >> >> > >> else's mainboard logs. > > > >>> > >> >> > >> > > > >>> > >> >> > >> On Wed, May 13, 2020 at 10:59 AM Keith Hui > > > >>> > >> >> > >> <buu...@gmail.com> wrote: > > > >>> > >> >> > >>> > > > >>> > >> >> > >>> Hi Aaron, > > > >>> > >> >> > >>> > > > >>> > >> >> > >>> It didn't help. There still a way out of whack entry in > > > >>> > >> >> > >>> the coreboot > > > >>> > >> >> > >>> table and e820 entry ending at 000003ffffffffff, which > > > >>> > >> >> > >>> I think have > > > >>> > >> >> > >>> more to do than the 41363's scope. > > > >>> > >> >> > >>> > > > >>> > >> >> > >>> Keith > > > >>> > >> >> > >>> > > > >>> > >> >> > >>> On Wed, May 13, 2020 at 12:24 PM Aaron Durbin > > > >>> > >> >> > >>> <adur...@google.com> wrote: > > > >>> > >> >> > >>> > > > > >>> > >> >> > >>> > I think the following patch will fix things up: > > > >>> > >> >> > >>> > https://review.coreboot.org/c/coreboot/+/41363 Please > > > >>> > >> >> > >>> > let me know. > > > >>> > >> >> > >>> > > > > >>> > >> >> > >>> > On Wed, May 13, 2020 at 8:43 AM Keith Hui > > > >>> > >> >> > >>> > <buu...@gmail.com> wrote: > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> Thanks Furquan. > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> Here are 3 logs. Log 1 is at the commit just before > > > >>> > >> >> > >>> >> the problem. Log 2 > > > >>> > >> >> > >>> >> is at the problem commit. Log 3 is at the current > > > >>> > >> >> > >>> >> master, if that's > > > >>> > >> >> > >>> >> what you meant by ToT. > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> I'm using SeaBIOS 1.13.0, compiled once using the > > > >>> > >> >> > >>> >> attached .config > > > >>> > >> >> > >>> >> before taking these logs. All 3 runs are taken using > > > >>> > >> >> > >>> >> the same SeaBIOS > > > >>> > >> >> > >>> >> binary. > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> Then I recompiled SeaBIOS with CONFIG_RELOCATE_INIT > > > >>> > >> >> > >>> >> off, replaced the > > > >>> > >> >> > >>> >> payload used in run 3, and took an extra run. In > > > >>> > >> >> > >>> >> this case the board > > > >>> > >> >> > >>> >> reset on its own at "Scanning option roms", looping > > > >>> > >> >> > >>> >> infinitely. > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> Hope this helps > > > >>> > >> >> > >>> >> Keith > > > >>> > >> >> > >>> >> > > > >>> > >> >> > >>> >> On Wed, May 13, 2020 at 7:38 AM Furquan Shaikh > > > >>> > >> >> > >>> >> <furquan.m.sha...@gmail.com> wrote: > > > >>> > >> >> > >>> >> > > > > >>> > >> >> > >>> >> > Thanks for the report Keith! > > > >>> > >> >> > >>> >> > > > > >>> > >> >> > >>> >> > On Wed, May 13, 2020 at 3:42 AM Paul Menzel > > > >>> > >> >> > >>> >> > <pmen...@molgen.mpg.de> wrote: > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Dear Keith, > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Am 13.05.20 um 05:21 schrieb Keith Hui: > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > I am still refining the P2B family of boards, > > > >>> > >> >> > >>> >> > > > now including the > > > >>> > >> >> > >>> >> > > > infamous P3B-F with an unusual appetite for > > > >>> > >> >> > >>> >> > > > hacks to make work. > > > >>> > >> >> > >>> >> > > > > > > >>> > >> >> > >>> >> > > > That said, I'm now finding that, on P3B-F, > > > >>> > >> >> > >>> >> > > > SeaBIOS hangs when it tries > > > >>> > >> >> > >>> >> > > > to relocate itself as part of its usual > > > >>> > >> >> > >>> >> > > > chores. Having just learned > > > >>> > >> >> > >>> >> > > > git bisect, I decided to try it out. > > > >>> > >> >> > >>> >> > > > > > > >>> > >> >> > >>> >> > > > It was commit > > > >>> > >> >> > >>> >> > > > 3b02006afe8a85477dafa1bd149f1f0dba02afc7 [1] > > > >>> > >> >> > >>> >> > > > that broke > > > >>> > >> >> > >>> >> > > > my SeaBIOS. It doesn't affect my newer toy the > > > >>> > >> >> > >>> >> > > > P8Z77-M as much as > > > >>> > >> >> > >>> >> > > > P3B-F, but I still want to blame that, and > > > >>> > >> >> > >>> >> > > > probably the very next > > > >>> > >> >> > >>> >> > > > commit as well, as they both deal with some > > > >>> > >> >> > >>> >> > > > very modern aspects of PCI > > > >>> > >> >> > >>> >> > > > that well predates the 440BX. > > > >>> > >> >> > >>> >> > > > > > > >>> > >> >> > >>> >> > > > Is there anything we can do to fix 3b02006afe? > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > I commented in the change-set [1] to make the > > > >>> > >> >> > >>> >> > > author and reviewers aware > > > >>> > >> >> > >>> >> > > of this issue and referenced your list message, > > > >>> > >> >> > >>> >> > > and ask to comment here. > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Could you please provide the debug log of > > > >>> > >> >> > >>> >> > > coreboot and SeaBIOS? > > > >>> > >> >> > >>> >> > > > > >>> > >> >> > >>> >> > As Paul mentioned, can you please provide the > > > >>> > >> >> > >>> >> > debug logs for coreboot > > > >>> > >> >> > >>> >> > and SeaBIOS both with ToT coreboot and with HEAD > > > >>> > >> >> > >>> >> > set before the change > > > >>> > >> >> > >>> >> > 3b02006afe where it does not hang? Thanks! > > > >>> > >> >> > >>> >> > > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > Meanwhile I ported the P3B-F board enable to > > > >>> > >> >> > >>> >> > > > flashrom [2], which got a > > > >>> > >> >> > >>> >> > > > heavy workout during this bisect, through > > > >>> > >> >> > >>> >> > > > vendor firmware and both > > > >>> > >> >> > >>> >> > > > good and bad builds of coreboot. In all cases > > > >>> > >> >> > >>> >> > > > I can flash internal, no > > > >>> > >> >> > >>> >> > > > longer having to haul out my P2B-LS just to > > > >>> > >> >> > >>> >> > > > use it as a flasher. > > > >>> > >> >> > >>> >> > > > > > > >>> > >> >> > >>> >> > > > Enjoy this long overdue board enable. If it > > > >>> > >> >> > >>> >> > > > gets submitted, I'll > > > >>> > >> >> > >>> >> > > > retract the ramstage hack[3] doing the same as > > > >>> > >> >> > >>> >> > > > redundant. > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Very nice! It’s always amazing, how after so > > > >>> > >> >> > >>> >> > > many years, when the vendor > > > >>> > >> >> > >>> >> > > already stopped supporting the device, the > > > >>> > >> >> > >>> >> > > community still supports the > > > >>> > >> >> > >>> >> > > device and improves the firmware showing that > > > >>> > >> >> > >>> >> > > Free Software is the more > > > >>> > >> >> > >>> >> > > sustainable way. > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Kind regards, > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > Paul > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > > > >>> > >> >> > >>> >> > > > [1] > > > >>> > >> >> > >>> >> > > > https://review.coreboot.org/c/coreboot/+/39486 > > > >>> > >> >> > >>> >> > > > [2] > > > >>> > >> >> > >>> >> > > > https://review.coreboot.org/c/flashrom/+/41354 > > > >>> > >> >> > >>> >> > > > [3] > > > >>> > >> >> > >>> >> > > > https://review.coreboot.org/c/coreboot/+/41224 > > > >>> > >> >> > >>> >> > > _______________________________________________ > > > >>> > >> >> > >>> >> > > coreboot mailing list -- coreboot@coreboot.org > > > >>> > >> >> > >>> >> > > To unsubscribe send an email to > > > >>> > >> >> > >>> >> > > coreboot-le...@coreboot.org > > > >>> > >> >> > >>> >> _______________________________________________ > > > >>> > >> >> > >>> >> coreboot mailing list -- coreboot@coreboot.org > > > >>> > >> >> > >>> >> To unsubscribe send an email to > > > >>> > >> >> > >>> >> coreboot-le...@coreboot.org > > > >>> > _______________________________________________ > > > >>> > coreboot mailing list -- coreboot@coreboot.org > > > >>> > To unsubscribe send an email to coreboot-le...@coreboot.org
USB coreboot-4.12-85-g39d16fd094-dirty Fri May 15 12:20:24 UTC 2020 bootblock starting (log level: 8)... Timestamp - end of bootblock: 1444519357 FMAP: Found "FLASH" version 1.1 at 0x0. FMAP: base = 0xff800000 size = 0x800000 #areas = 3 FMAP: area COREBOOT found @ 200 (8388096 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 30000 size 5f254 Timestamp - starting to load romstage: 1469221515 Timestamp - finished loading romstage: 1474033292 BS: bootblock times (exec / console): total (unknown) / 22 ms coreboot-4.12-85-g39d16fd094-dirty Fri May 15 12:20:24 UTC 2020 romstage starting (log level: 8)... APIC 00: CPU Family_Model = 00700f01 APIC 00: ** Enter AmdInitReset [00020007] Timestamp - calling AmdInitReset: 1506488712 Fch OEM config in INIT RESET FMAP: area COREBOOT found @ 200 (8388096 bytes) CBFS: Locating 'cmos_layout.bin' CBFS: Found @ offset 2300 size 3a0 Force SATA 3Gbps mode = 0 Timestamp - back from AmdInitReset: 1534188611 AmdInitReset() returned AGESA_SUCCESS APIC 00: Heap in LocalCache (2) at 0x00400000 APIC 00: ** Exit AmdInitReset [00020007] APIC 00: ** Enter AmdInitEarly [00020002] Timestamp - calling AmdInitEarly: 1555806675 Timestamp - back from AmdInitEarly: 4064588828 AmdInitEarly() returned AGESA_SUCCESS APIC 00: Heap in LocalCache (2) at 0x00400000 APIC 00: ** Exit AmdInitEarly [00020002] Timestamp - before RAM initialization: 4105454993 APIC 00: ** Enter AmdInitPost [00020006] Timestamp - calling AmdInitPost: 4128924296 -------------READING SPD----------- iobase: 0x00000B00, SmbusSlave: 0x000000A0, count: 256 -------------SPD READ ERROR----------- -------------READING SPD----------- iobase: 0x00000B00, SmbusSlave: 0x000000A2, count: 256 -------------FINISHED READING SPD----------- Timestamp - back from AmdInitPost: 9821308201 AmdInitPost() returned AGESA_SUCCESS APIC 00: Heap in TempMem (3) at 0x000b0000 APIC 00: ** Exit AmdInitPost [00020006] Timestamp - after RAM initialization: 9865497577 CBMEM: IMD: root @ 0x5ffff000 254 entries. IMD: root @ 0x5fffec00 62 entries. MTRR Range: Start=0 End=40000000 (Size 40000000) MTRR Range: Start=40000000 End=60000000 (Size 20000000) MTRR Range: Start=ff800000 End=0 (Size 800000) FMAP: area COREBOOT found @ 200 (8388096 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 11180 size 56e8 Decompressing stage fallback/postcar @ 0x5ffbafc0 (38544 bytes) Loading module at 0x5ffbb000 with entry 0x5ffbb000. filesize: 0x52d0 memsize: 0x9650 Processing 239 relocs. Offset value of 0x5dfbb000 Timestamp - end of romstage: 10016518336 BS: romstage times (exec / console): total (unknown) / 71 ms usbdebug: postcar starting... Timestamp - start of postcar: 10065510791 Timestamp - end of postcar: 10074287506 FMAP: area COREBOOT found @ 200 (8388096 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 8f2c0 size 2643b Timestamp - starting to load ramstage: 10108046641 Decompressing stage fallback/ramstage @ 0x5fe84fc0 (1264816 bytes) Timestamp - starting LZMA decompress (ignore for x86): 10132199800 Timestamp - finished LZMA decompress (ignore for x86): 10294920822 Loading module at 0x5fe85000 with entry 0x5fe85000. filesize: 0x54ac8 memsize: 0x134c70 Processing 6591 relocs. Offset value of 0x5f085000 Timestamp - finished loading ramstage: 10336701589 BS: postcar times (exec / console): total (unknown) / 36 ms usbdebug: ramstage starting... Timestamp - start of ramstage: 10386257221 Normal boot APIC 00: ** Enter AmdInitEnv [00020003] Timestamp - calling AmdInitEnv: 10406816125 Wiped HEAP at [10000000 - 1002ffff] Fch OEM config in INIT ENV IDE2AHCI = 0 Timestamp - back from AmdInitEnv: 10445958874 AmdInitEnv() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdInitEnv [00020003] BS: BS_PRE_DEVICE entry times (exec / console): 3 / 16 ms Timestamp - device enumeration: 10491771478 BS: BS_DEV_INIT_CHIPS run times (exec / console): 0 / 2 ms Enumerating buses... Mainboard AM1I-A Enable. Root Device scanning... setup_bsp_ramtop, TOP MEM: msr.lo = 0x80000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x80000000, msr.hi = 0x00000002 CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled CPU_CLUSTER: 0 scanning... CPU: APIC: 00 enabled CPU: APIC: 01 enabled CPU: APIC: 02 enabled CPU: APIC: 03 enabled scan_bus: bus CPU_CLUSTER: 0 finished in 4 msecs DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [1022/1536] enabled PCI: 00:01.0 [1002/9830] enabled PCI: 00:01.1 [1002/9840] enabled PCI: 00:02.0 [1022/1538] enabled PCI: 00:02.1 subordinate bus PCI Express PCI: 00:02.1 [1022/1439] enabled PCI: 00:02.5 subordinate bus PCI Express PCI: 00:02.5 [1022/1439] enabled hudson_enable() PCI: Static device PCI: 00:10.0 not found, disabling it. hudson_enable() PCI: 00:11.0 [1022/7800] enabled hudson_enable() PCI: 00:12.0 [1022/7807] enabled hudson_enable() PCI: 00:12.2 [1022/7808] enabled hudson_enable() PCI: 00:13.0 [1022/7807] enabled hudson_enable() PCI: 00:13.2 [1022/7808] enabled hudson_enable() PCI: 00:14.0 [1022/780b] enabled hudson_enable() PCI: 00:14.2 [1022/780d] enabled hudson_enable() PCI: 00:14.3 [1022/780e] enabled hudson_enable() hudson_enable() PCI: 00:16.0 [1022/7807] enabled hudson_enable() PCI: 00:16.2 [1022/7808] enabled PCI: 00:18.0 [1022/1530] enabled PCI: 00:18.1 [1022/1531] enabled PCI: 00:18.2 [1022/1532] enabled PCI: 00:18.3 [1022/1533] enabled PCI: 00:18.4 [1022/1534] enabled PCI: 00:18.5 [1022/1535] enabled PCI: Leftover static devices: PCI: 00:02.2 PCI: 00:02.3 PCI: 00:02.4 PCI: 00:10.0 PCI: 00:14.7 PCI: Check your devicetree.cb. PCI: 00:02.1 scanning... PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1002/67df] enabled PCI: 01:00.1 [1002/aaf0] enabled Enabling Common Clock Configuration ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 256 Enabling Common Clock Configuration ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 256 scan_bus: bus PCI: 00:02.1 finished in 13 msecs PCI: 00:02.5 scanning... PCI: pci_scan_bus for bus 02 PCI: 02:00.0 [10ec/8168] enabled Enabling Common Clock Configuration ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:02.5 finished in 7 msecs PCI: 00:14.0 scanning... scan_bus: bus PCI: 00:14.0 finished in 0 msecs PCI: 00:14.3 scanning... PNP: 002e.0 disabled PNP: 002e.1 enabled PNP: 002e.2 enabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 enabled PNP: 002e.6 enabled PNP: 002e.7 enabled PNP: 004e.0 enabled scan_bus: bus PCI: 00:14.3 finished in 8 msecs scan_bus: bus DOMAIN: 0000 finished in 103 msecs scan_bus: bus Root Device finished in 123 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 129 ms Timestamp - device configuration: 11093672470 found VGA at PCI: 00:01.0 found VGA at PCI: 01:00.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... fx_devs=0x1 node 0: mmio_basek=00200000, basek=00400000, limitk=009e0000 add_uma_resource_below_tolm: uma size 0x20000000, memory start 0x60000000 Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. More than one caller of pci_ehci_read_resources from PCI: 00:12.0 PCI: 00:12.2 EHCI BAR hook registered More than one caller of pci_ehci_read_resources from PCI: 00:13.0 More than one caller of pci_ehci_read_resources from PCI: 00:13.2 More than one caller of pci_ehci_read_resources from PCI: 00:16.0 More than one caller of pci_ehci_read_resources from PCI: 00:16.2 Done reading resources. Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) Resource ranges: Base: 1000, Size: f000, Tag: 100 Resource ranges: Base: a0000, Size: 20000, Tag: 200 Base: 80000000, Size: 78000000, Tag: 200 Base: fc000000, Size: 2d40000, Tag: 200 Base: fed45000, Size: 12bb000, Tag: 200 Base: 280000000, Size: fd80000000, Tag: 100200 Resource ranges: Base: 1000, Size: 1000, Tag: 100 Resource ranges: Base: 80000000, Size: 10200000, Tag: 1200 Resource ranges: Base: ff800000, Size: 100000, Tag: 200 Resource ranges: Base: 2000, Size: 1000, Tag: 100 Resource ranges: Base: ff900000, Size: 100000, Tag: 1200 Resource ranges: Base: ffa00000, Size: 100000, Tag: 200 PCI: 00:01.0 10 <- [0x00a0000000 - 0x00afffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:01.0 18 <- [0x00ff000000 - 0x00ff7fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000003000 - 0x00000030ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00ffb00000 - 0x00ffb3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00ffb40000 - 0x00ffb5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00ffb60000 - 0x00ffb63fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.1 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:02.1 24 <- [0x0080000000 - 0x00901fffff] size 0x10200000 gran 0x14 bus 01 prefmem PCI: 00:02.1 20 <- [0x00ff800000 - 0x00ff8fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 01:00.0 18 <- [0x0090000000 - 0x00901fffff] size 0x00200000 gran 0x15 prefmem64 PCI: 01:00.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 24 <- [0x00ff800000 - 0x00ff83ffff] size 0x00040000 gran 0x12 mem PCI: 01:00.0 30 <- [0x00ff840000 - 0x00ff85ffff] size 0x00020000 gran 0x11 romem PCI: 01:00.1 10 <- [0x00ff860000 - 0x00ff863fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.5 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io PCI: 00:02.5 24 <- [0x00ff900000 - 0x00ff9fffff] size 0x00100000 gran 0x14 bus 02 prefmem PCI: 00:02.5 20 <- [0x00ffa00000 - 0x00ffafffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 02:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 02:00.0 18 <- [0x00ffa00000 - 0x00ffa00fff] size 0x00001000 gran 0x0c mem64 PCI: 02:00.0 20 <- [0x00ff900000 - 0x00ff903fff] size 0x00004000 gran 0x0e prefmem64 PCI: 00:11.0 10 <- [0x0000005000 - 0x0000005007] size 0x00000008 gran 0x03 io PCI: 00:11.0 14 <- [0x0000007000 - 0x0000007003] size 0x00000004 gran 0x02 io PCI: 00:11.0 18 <- [0x0000006000 - 0x0000006007] size 0x00000008 gran 0x03 io PCI: 00:11.0 1c <- [0x0000008000 - 0x0000008003] size 0x00000004 gran 0x02 io PCI: 00:11.0 20 <- [0x0000004000 - 0x000000400f] size 0x00000010 gran 0x04 io PCI: 00:11.0 24 <- [0x00ffb6b000 - 0x00ffb6b3ff] size 0x00000400 gran 0x0a mem PCI: 00:12.0 10 <- [0x00ffb68000 - 0x00ffb68fff] size 0x00001000 gran 0x0c mem PCI: 00:12.2 EHCI Debug Port hook triggered PCI: 00:<- [0x00ffb6c000 - 0x00ffb6c0ff] size 0x00000100 gran 0x08 mem PCI: 00:12.2 EHCI Debug Port relocated PCI: 00:13.0 10 <- [0x00ffb69000 - 0x00ffb69fff] size 0x00001000 gran 0xPCI: 00:13.2 10 <- [0x00ffb6d000 - 0x00ffb6d0ff] size 0x00000100 gran 0x08 mem PCI: 00:14.2 10 <- [0x00ffb64000 - 0x00ffb67fff] size 0x00004000 gran 0x0e mem64 PNP: 002- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x0PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002- [0x0000000778 - 0x000000077f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x000- 0x0000000005] size 0x00000001 gran 0x00 irq PNP: 002e.3 74 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 drq PNP: 002e.4 60 <- [0x0000000290 - 0x000000029f] size 0x00000010 gran 0x04 io PNP: 002- [0x0000000230 - 0x000000023f] size 0x00000010 gran 0x04 io ERROR: PNP: 002e.4 70 irq size: 0x0000000001 not assigned in devicetree PNP: 002- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io PNP: 002- [0x0000000064 000064] size 0x00000001 gran 0x00 io PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x0gran 0x00 irq PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq PNP: 002e.7 60 <- [0x0000000320 - 0x0000000320] size 0x00000001 gran 0x00 io PNP: 002e.7 62 <0000300 00031f] size 0x00000020 gran 0x05 io PNP: 002e.7 64 <- [0x0000000321 - 0x0000000321] size 0x00000001 gran 0x00 io ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned in dev PCI: 00:16.0 10 <- [0x00ffb6a000 - 0x00ffb6afff] size 0x000010000c mem PCI: 00:16.2 10 <- [0x00ffb6e000 - 0x00ffb6e0ff] size 0x00000100 gran 0x08 mem Done setting resources. resourceBS: BS_DEV_RESOURCES run times (exec / console): 0 / 275 ms APIC 0ter AmdInitMid [00020005] Timestaming AmdInitMid: 12325669775 USB ... boot loop here ...
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index cedc7dae06..0467b27586 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -683,6 +683,8 @@ static void domain_set_resources(struct device *dev) u32 reset_memhole = 1; #endif + domain_read_resources(dev); + pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -768,11 +770,13 @@ static void domain_set_resources(struct device *dev) add_uma_resource_below_tolm(dev, 7); +/* for (link = dev->link_list; link; link = link->next) { if (link->children) { assign_resources(link); } } +*/ } static const char *domain_acpi_name(const struct device *dev) @@ -784,8 +788,8 @@ static const char *domain_acpi_name(const struct device *dev) } static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, + .read_resources = domain_set_resources, + .set_resources = pci_domain_set_resources, .scan_bus = pci_domain_scan_bus, .acpi_name = domain_acpi_name, };
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