Hi, On Mon, Nov 9, 2020 at 6:42 PM <j...@gmx.com> wrote: > > Hello! I'm trying to find if my hardware supports Coreboot. I found 1 table > which is retired, second that is probably not retired and then current > documentation that doesn't seem to say as much. So, sorry if I missed it. > Will Coreboot work with HP ProLiant DL360e Gen8? Flashrom worked ok but not > great. Northbridge is Intel Sandy Bridge-E 07, Southbridge Intel X79 05.
Short answer: Nope. Long answer: Porting this board would be extremely time-consuming (several years for an experienced developer working exclusively on it), because there's no support at all for the chipset. While there's support for mundane Sandy (and Ivy) Bridge consumer (desktop, mobile, uniprocessor server) hardware, the SA and PCH (System Agent and Platform Controller Hub, i.e. integrated northbridge and southbridge respectively) on server platforms are radically different beasts. Memory initialization is by far the most complex thing that would need to be implemented, and the registers aren't publicly documented and differ across generations, as well as between consumer and server platforms. > References: > https://www.coreboot.org/Supported_Chipsets_and_Devices > https://coreboot.org/status/board-status.html > https://support.hpe.com/hpesc/public/docDisplay?docId=c03361169&docLocale=en_US > https://browser.geekbench.com/geekbench3/1879558 > https://doc.coreboot.org/mainboard/index.html > https://doc.coreboot.org/northbridge/intel/sandybridge/index.html > > Flashrom log: > ------------------------ > flashrom v1.2 on Linux 5.4.0-42-generic (x86_64) > flashrom is free software, get the source code at https://flashrom.org > > Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). > Found chipset "Intel C60x/X79". > Enabling flash write... FREG0: Flash Descriptor region > (0x00000000-0x0000ffff) is read-only. > FREG2: Management Engine region (0x00010000-0x001fffff) is locked. > Not all flash regions are freely accessible by flashrom. This is most likely > due to an active ME. Please see https://flashrom.org/ME for details. > At least some flash regions are read protected. You have to use a flash > layout and include only accessible regions. For write operations, you'll > additionally need the --noverify-all switch. See manpage for more details. > OK. > Found Macronix flash chip "MX25L1605" (2048 kB, SPI) mapped at physical > address 0x00000000ffe00000. > Found Macronix flash chip "MX25L1605A/MX25L1606E/MX25L1608E" (2048 kB, SPI) > mapped at physical address 0x00000000ffe00000. > Found Macronix flash chip "MX25L1605D/MX25L1608D/MX25L1673E" (2048 kB, SPI) > mapped at physical address 0x00000000ffe00000. > Multiple flash chip definitions match the detected chip(s): "MX25L1605", > "MX25L1605A/MX25L1606E/MX25L1608E", "MX25L1605D/MX25L1608D/MX25L1673E" > Please specify which chip definition to use with the -c <chipname> option. This is expected for this kind of platform, since the IFD (Intel Flash Descriptor) specifies the regions of the flash chip and their access permissions. > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org Regards, Angel _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
