[coreboot] Re: coreboot image forIntel Harcuvar CRB

[Szafranski, MariuszX]

Hi Tirumalesh,

Please verify if FSP is correctly integrated. Especially if FSP-T part is 
enabled and used for setting up CAR.
config mainboard section:
vendor->Intel,
model->Harcuvar,
romsize ->16M, (insert your actual SPI flash size)
cbfs size 8M (0x800000) (or adjust for your needs)
config chipset:
                check  Enable High-speed UART debug port selected by 
UART_FOR_CONSOLE (enable for non legacy UART mode, disable for legacy)
                cache as ram implementation -> Use FSP CAR
                UART mode – leave at default non legacy mode (or enable if 
needed – adjust other settings for legacy mode)
                Verify if generate from tree is selected for microcode (Include 
CPU microcode in CBFS (Generate from tree))
config generic drivers:
                UART's PCI bus, device, function address - 0x8000d000
                Verify if “serial port” on superior is unchecked (need to be 
when using UART in legacy mode)
config console:
                verify if two first options (bootblock console and postcar 
console) are enabled

As I remember there are two serial port connectors – check if you are using 
correct one (try both)

BR,
Mariusz

From: Tirumalesh <tirumal...@chalamarla.com>
Sent: Friday, February 5, 2021 8:54 AM
To: Javier Galindo <javiergali...@sysproconsulting.com>; coreboot@coreboot.org
Subject: [coreboot] Re: coreboot image forIntel Harcuvar CRB

It seems the FSP binaries are auto included, and the configs seems to be of no 
effect.
Is it not right?

If so I will try to add binaries and microcode header file.

Thanks,
Tirumalesh


On Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo 
<javiergali...@sysproconsulting.com<mailto:javiergali...@sysproconsulting.com>> 
wrote:
Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y

Also have you setup all the proper fsp/ucode binaries that are commented out in 
the config file (just did a quick review):

#Sample settings for Denverton-NS FSP.
#CONFIG_ADD_FSP_BINARIES=y
#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
#CONFIG_FSP_CAR=y

#Sample settings for microcode definitions.
#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y

Unfortunately all my harcuvar work has also been on a fairly old tree of 
coreboot.

I'll give it a try on my Harcuvar if you don't make any progress, but it won't 
be until the weekend.
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