https://review.coreboot.org/c/coreboot/+/29398 Have similar implementation on braswell, so as long as sc_init get executed in ramstage the serial irq mode programming shall be working.
Zhiwen Zheng <zhi...@40701.xyz> 于2021年11月6日周六 下午6:29写道： > I add the following code to sc_init() in southcluster.c to enable SERIRQ, > and it works as expected when doing cold boot. With SERIRQ enabled, the > uart in superio can function correctly, and I can login into the linux > serial console. But after a reboot initiated from linux cmdline, the linux > boot hang in getty serial(same as without SERIRQ enabled), only a power > cycle can resolve the issue. I take the following code from coreboot-4.11 > fsp-baytrail. I also tried the check_for_warm_reset() in bootblock.c to > hardreset the machine, but the check condition in that procedure doesn't > catch this situation, linux reset by default use keyboard controller > seemingly. > > u32 *oic = (u32 *)(ILB_BASE_ADDRESS + 0x60); > u8 *serirq_cntl = (u8 *)(ILB_BASE_ADDRESS + 0x10); > > > /* Enable SERIRQ */ > write32(oic, (read32(oic) | (1 << 12))); > /* Enable continuous mode */ > write8(serirq_cntl, (1 << 7)); > _______________________________________________ > coreboot mailing list -- coreboot@coreboot.org > To unsubscribe send an email to coreboot-le...@coreboot.org >
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