Hi Keith Thanks a lot for testing! It looks like the newer parallel mp code uses "mfence" which is probably not supported by your CPU. I updated the code to reflect that. I'd appreciate if you can test the latest version of https://review.coreboot.org/c/coreboot/+/59693/
Kind regards On Tue, Nov 30, 2021 at 8:13 PM Keith Hui <[email protected]> wrote: > Hi everyone, > > Thanks for your efforts to keep a computing legend alive. :) > > I suffered an unexpected exception after applying the patch train. > Serial log at the end of this email. I probably could leave out > bootblock/romstage/postcar, but it's here for completeness. Next: > bisect. > > I do still have a P2B-DS on hand, but all my Pentium 3 CPUs are > singles, and Pentium III-S 1400MHz (the best CPU money can buy for > this board) are running ~$85 apiece on ebay. On the other hand, I > think one of my two P2B-LS may have died. > > (Branden - and a P3B-F board too. ;-) > > Meanwhile, I should have pushed harder to get P8Z77-M into the tree. > > Keith > > On Tue, 30 Nov 2021 at 05:32, Angel Pons <[email protected]> wrote: > > > > Hi Branden, > > > > On Mon, Nov 29, 2021 at 9:18 PM Branden Waldner <[email protected]> > wrote: > > > > > > I wasn't really sure that I wanted to comment on this, but seeing as > > > how I have some of the affected boards I guess I should. > > > > Thank you very much. > > > > > Angel Pons wrote: > > > > Besides AMD AGESA boards, the other boards that need to be updated > are AOpen DXPL > > > > Plus-U (a dual-socket server board that uses Netburst Xeons, no > other board in the tree uses > > > > the same chipset code) and various Asus P2B boards (which support > Pentium 2/3 CPUs, these > > > > boards are older than me). Even though I only know two people who > still have some of these > > > > boards (and they don't have the same boards), they're still > supported because the code has > > > > been maintained so far. > > > > > > I am one of the two with Asus P2B boards, with Keith Hui being the > > > other. I've got a P2B and a P2-99 and I believe Keith Hui has a > > > P2B-LS. > > > So far there have not been very many changes and Keith Hui and others > > > have worked on them, all I've done is test master and relevant patch > > > sets every once in a while. > > > I know I have not been uploading board_status results and I have not > > > gotten around to fixing the variant set up for the P2-99 so I'm not > > > uploading results that are uncertain about which board they are for. > > > Not really relevant, but I think it is pretty neat to be running > > > coreboot on boards older then some of the contributors. > > > > > > Mike Banon wrote: > > > > I am often build-testing my boards (didn't notice a > > > > https://review.coreboot.org/c/coreboot/+/59636 problem for a while, > but only because I've been > > > > re-using the previously built toolchains to save time). Also, I am > actively tech-supporting all the > > > > people who would like to build coreboot for AMD boards from this > list, even right now I am in an > > > > active message exchange with >10 people who are switching to these > boards to run coreboot > > > > on them - and any user may give back to the project one day. > > > > > > I actually have a few AMD boards and laptops that might be viable for > > > porting to, but I've never looked in to it much because of the state > > > support is in coreboot and the fact most of the hardware was actively > > > being used. > > > > > > Arthur Heymans wrote: > > > > The first one I'd like to deprecate is LEGACY_SMP_INIT. This also > includes the codepath for > > > > SMM_ASEG. This code is used to start APs and do some feature > programming on each AP, but > > > > also set up SMM. This has largely been superseded by PARALLEL_MP, > which should be able > > > > to cover all use cases of LEGACY_SMP_INIT, with little code changes. > The reason for > > > > deprecation is that having 2 codepaths to do the virtually the same > increases maintenance > > > > burden on the community a lot, while also being rather confusing. > > > > > > > > A few things are lacking in PARALLEL_MP init: - Support for > !CONFIG_SMP on single core > > > > systems. It's likely easy to extend PARALLEL_MP or write some code > that just does CPU > > > > detection on the BSP CPU. - Support smm in the legacy ASEG (0xa0000 > - 0xb0000) region. A > > > > POC showed that it's not that hard to do with PARALLEL_MP > > > > https://review.coreboot.org/c/coreboot/+/58700 > > > > > > I didn't even know that was a problem until now. I doubt there is much > > > I can do about it myself at this point in time, though I can try to > > > look through it I guess. > > > > Looks like Arthur has already implemented some changes to use > > PARALLEL_MP on i440bx. As of writing, the patches assume there's only > > one CPU (I already pointed out this is incorrect for boards with two > > CPU sockets/slots). I'd greatly appreciate if Keith and/or you could > > test them on actual hardware. The patches to apply, in order, are: > > > > https://review.coreboot.org/59694 > > https://review.coreboot.org/59695 > > https://review.coreboot.org/59692 > > https://review.coreboot.org/59693 > > > > > Branden Waldner > > > > Best regards, > > Angel > > coreboot-4.15-346-g096d97c3c6-dirty Tue Nov 30 17:10:13 UTC 2021 > bootblock starting (log level: 7)... > FMAP: Found "FLASH" version 1.1 at 0x0. > FMAP: base = 0xfffc0000 size = 0x40000 #areas = 3 > FMAP: area COREBOOT found @ 200 (261632 bytes) > CBFS: Found 'fallback/romstage' @0x80 size 0x4588 > BS: bootblock times (exec / console): total (unknown) / 28 ms > PROG_RUN: Setting MTRR to cache XIP stage. base: 0xfffc0000, size: > 0x00008000 > > > coreboot-4.15-346-g096d97c3c6-dirty Tue Nov 30 17:10:13 UTC 2021 > romstage starting (log level: 7)... > Romstage stack size limited to 0x1000! > SMBus controller enabled > CBMEM: > IMD: root @ 0x2ffff000 254 entries. > IMD: root @ 0x2fffec00 62 entries. > MTRR Range: Start=2f800000 End=30000000 (Size 800000) > MTRR Range: Start=fffc0000 End=0 (Size 40000) > FMAP: area COREBOOT found @ 200 (261632 bytes) > CBFS: Found 'fallback/postcar' @0x19b40 size 0x4244 > Loading module at 0x2ffd3000 with entry 0x2ffd3031. filesize: 0x3fe0 > memsize: 0x82d0 > Processing 137 relocs. Offset value of 0x2dfd3000 > BS: romstage times (exec / console): total (unknown) / 54 ms > > > coreboot-4.15-346-g096d97c3c6-dirty Tue Nov 30 17:10:13 UTC 2021 > postcar starting (log level: 7)... > FMAP: area COREBOOT found @ 200 (261632 bytes) > CBFS: Found 'fallback/ramstage' @0xaf00 size 0xcc31 > Loading module at 0x2ffad000 with entry 0x2ffad000. filesize: 0x19118 > memsize: 0x246e8 > Processing 1656 relocs. Offset value of 0x2f1ad000 > BS: postcar times (exec / console): total (unknown) / 30 ms > > > coreboot-4.15-346-g096d97c3c6-dirty Tue Nov 30 17:10:13 UTC 2021 > ramstage starting (log level: 7)... > Enumerating buses... > Root Device scanning... > CPU_CLUSTER: 0 enabled > DOMAIN: 0000 enabled > DOMAIN: 0000 scanning... > PCI: pci_scan_bus for bus 00 > PCI: 00:00.0 [8086/7190] enabled > PCI: 00:01.0 [8086/7191] enabled > PCI: 00:04.0 [8086/7110] enabled > PCI: 00:04.1 [8086/7111] enabled > PCI: 00:04.2 [8086/7112] enabled > PCI: 00:04.3 [8086/7113] enabled > PCI: 00:06.0 [9005/001f] enabled > PCI: 00:07.0 [8086/1229] enabled > PCI: 00:01.0 scanning... > PCI: pci_scan_bus for bus 01 > PCI: 01:00.0 [10de/0322] enabled > scan_bus: bus PCI: 00:01.0 finished in 5 msecs > PCI: 00:04.0 scanning... > PNP: 03f0.0 enabled > PNP: 03f0.1 enabled > PNP: 03f0.2 enabled > PNP: 03f0.3 enabled > PNP: 03f0.5 enabled > PNP: 03f0.7 enabled > PNP: 03f0.8 enabled > PNP: 03f0.a disabled > scan_bus: bus PCI: 00:04.0 finished in 14 msecs > PCI: 00:04.3 scanning... > scan_bus: bus PCI: 00:04.3 finished in 0 msecs > scan_bus: bus DOMAIN: 0000 finished in 66 msecs > scan_bus: bus Root Device finished in 76 msecs > done > BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 85 ms > found VGA at PCI: 01:00.0 > A bridge on the path doesn't support 16-bit VGA decoding!Setting up > VGA for PCI: 01:00.0 > Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 > Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 > Setting PCI_BRIDGE_CTL_VGA for bridge Root Device > Allocating resources... > Reading resources... > Setting RAM size to 768 MB > PNP: 03f0.8 missing read_resources > Done reading resources. > === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === > PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff > PCI: 00:01.0 io: size: 0 align: 12 gran: 12 limit: ffff done > PCI: 00:01.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff > PCI: 01:00.0 10 * [0x0 - 0xffffff] mem > PCI: 01:00.0 30 * [0x1000000 - 0x101ffff] mem > PCI: 00:01.0 mem: size: 1100000 align: 24 gran: 20 limit: ffffffff done > PCI: 00:01.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffff > PCI: 01:00.0 14 * [0x0 - 0x7ffffff] prefmem > PCI: 00:01.0 prefmem: size: 8000000 align: 27 gran: 20 limit: ffffffff > done > === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === > DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff > update_constraints: PCI: 00:04.0 01 base 00000000 limit 00000fff io > (fixed) > update_constraints: PNP: 03f0.0 60 base 000003f0 limit 000003f7 io (fixed) > update_constraints: PNP: 03f0.1 60 base 00000378 limit 0000037f io (fixed) > update_constraints: PNP: 03f0.2 60 base 000003f8 limit 000003ff io (fixed) > update_constraints: PNP: 03f0.3 60 base 000002f8 limit 000002ff io (fixed) > update_constraints: PNP: 03f0.5 60 base 00000060 limit 00000060 io (fixed) > update_constraints: PNP: 03f0.5 62 base 00000064 limit 00000064 io (fixed) > update_constraints: PNP: 03f0.7 60 base 00000000 limit 00000000 io (fixed) > update_constraints: PNP: 03f0.7 62 base 00000000 limit 00000001 io (fixed) > update_constraints: PCI: 00:04.3 01 base 0000e400 limit 0000e43f io > (fixed) > update_constraints: PCI: 00:04.3 02 base 00000f00 limit 00000f0f io > (fixed) > DOMAIN: 0000: Resource ranges: > * Base: 1000, Size: d400, Tag: 100 > * Base: e440, Size: 1bc0, Tag: 100 > PCI: 00:06.0 10 * [0x1000 - 0x10ff] limit: 10ff io > PCI: 00:04.2 20 * [0x1100 - 0x111f] limit: 111f io > PCI: 00:07.0 14 * [0x1120 - 0x113f] limit: 113f io > PCI: 00:04.1 20 * [0x1140 - 0x114f] limit: 114f io > DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done > DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff > update_constraints: DOMAIN: 0000 0a base 00000000 limit 0009ffff mem > (fixed) > update_constraints: DOMAIN: 0000 0b base 000c0000 limit 2fffffff mem > (fixed) > update_constraints: PCI: 00:04.0 02 base ff800000 limit ffffffff mem > (fixed) > update_constraints: PCI: 00:04.0 03 base fec00000 limit fec00fff mem > (fixed) > DOMAIN: 0000: Resource ranges: > * Base: a0000, Size: 20000, Tag: 200 > * Base: 30000000, Size: cec00000, Tag: 200 > * Base: fec01000, Size: bff000, Tag: 200 > * Base: 100000000, Size: f00000000, Tag: 100200 > PCI: 00:00.0 10 * [0x30000000 - 0x3fffffff] limit: 3fffffff prefmem > PCI: 00:01.0 24 * [0x40000000 - 0x47ffffff] limit: 47ffffff prefmem > PCI: 00:01.0 20 * [0x48000000 - 0x490fffff] limit: 490fffff mem > PCI: 00:07.0 18 * [0x49100000 - 0x491fffff] limit: 491fffff mem > PCI: 00:07.0 30 * [0x49200000 - 0x492fffff] limit: 492fffff mem > PCI: 00:06.0 30 * [0xa0000 - 0xbffff] limit: bffff mem > PCI: 00:06.0 14 * [0x49300000 - 0x49300fff] limit: 49300fff mem > PCI: 00:07.0 10 * [0x49301000 - 0x49301fff] limit: 49301fff prefmem > DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done > PCI: 00:01.0 prefmem: base: 40000000 size: 8000000 align: 27 gran: 20 > limit: 47ffffff > PCI: 00:01.0: Resource ranges: > * Base: 40000000, Size: 8000000, Tag: 1200 > PCI: 01:00.0 14 * [0x40000000 - 0x47ffffff] limit: 47ffffff prefmem > PCI: 00:01.0 prefmem: base: 40000000 size: 8000000 align: 27 gran: 20 > limit: 47ffffff done > PCI: 00:01.0 mem: base: 48000000 size: 1100000 align: 24 gran: 20 > limit: 490fffff > PCI: 00:01.0: Resource ranges: > * Base: 48000000, Size: 1100000, Tag: 200 > PCI: 01:00.0 10 * [0x48000000 - 0x48ffffff] limit: 48ffffff mem > PCI: 01:00.0 30 * [0x49000000 - 0x4901ffff] limit: 4901ffff mem > PCI: 00:01.0 mem: base: 48000000 size: 1100000 align: 24 gran: 20 > limit: 490fffff done > === Resource allocator: DOMAIN: 0000 - resource allocation complete === > PCI: 00:00.0 10 <- [0x0030000000 - 0x003fffffff] size 0x10000000 gran > 0x1c prefmem > PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran > 0x0c bus 01 io > PCI: 00:01.0 24 <- [0x0040000000 - 0x0047ffffff] size 0x08000000 gran > 0x14 bus 01 prefmem > PCI: 00:01.0 20 <- [0x0048000000 - 0x00490fffff] size 0x01100000 gran > 0x14 bus 01 mem > PCI: 01:00.0 10 <- [0x0048000000 - 0x0048ffffff] size 0x01000000 gran 0x18 > mem > PCI: 01:00.0 14 <- [0x0040000000 - 0x0047ffffff] size 0x08000000 gran > 0x1b prefmem > PCI: 01:00.0 30 <- [0x0049000000 - 0x004901ffff] size 0x00020000 gran 0x11 > romem > PNP: 03f0.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 > io > PNP: 03f0.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 > irq > PNP: 03f0.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 > drq > PNP: 03f0.1 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 > io > PNP: 03f0.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 > irq > PNP: 03f0.1 74 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 > drq > PNP: 03f0.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 > io > PNP: 03f0.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 > irq > PNP: 03f0.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 > io > PNP: 03f0.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 > irq > PNP: 03f0.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 > io > PNP: 03f0.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 > io > PNP: 03f0.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 > irq > PNP: 03f0.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 > irq > PNP: 03f0.7 60 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 > io > PNP: 03f0.7 62 <- [0x0000000000 - 0x0000000001] size 0x00000002 gran 0x01 > io > PNP: 03f0.7 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 > irq > PCI: 00:04.1 20 <- [0x0000001140 - 0x000000114f] size 0x00000010 gran 0x04 > io > PCI: 00:04.2 20 <- [0x0000001100 - 0x000000111f] size 0x00000020 gran 0x05 > io > PCI: 00:06.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 > io > PCI: 00:06.0 14 <- [0x0049300000 - 0x0049300fff] size 0x00001000 gran 0x0c > mem64 > PCI: 00:06.0 30 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x11 > romem > PCI: 00:07.0 10 <- [0x0049301000 - 0x0049301fff] size 0x00001000 gran > 0x0c prefmem > PCI: 00:07.0 14 <- [0x0000001120 - 0x000000113f] size 0x00000020 gran 0x05 > io > PCI: 00:07.0 18 <- [0x0049100000 - 0x00491fffff] size 0x00100000 gran 0x14 > mem > PCI: 00:07.0 30 <- [0x0049200000 - 0x00492fffff] size 0x00100000 gran 0x14 > romem > Done setting resources. > Done allocating resources. > BS: BS_DEV_RESOURCES run times (exec / console): 0 / 618 ms > Enabling resources... > PCI: 00:00.0 cmd <- 06 > PCI: 00:01.0 bridge ctrl <- 009b > PCI: 00:01.0 cmd <- 07 > PCI: 00:04.0 cmd <- 07 > PCI: 00:04.1 cmd <- 01 > PCI: 00:04.2 cmd <- 01 > PCI: 00:04.3 cmd <- 01 > PCI: 00:06.0 cmd <- 03 > PCI: 00:07.0 cmd <- 03 > PCI: 01:00.0 cmd <- 03 > done. > BS: BS_DEV_ENABLE run times (exec / console): 0 / 24 ms > Initializing devices... > CPU_CLUSTER: 0 init > CPU: Intel(R) Celeron(TM) CPU 1400MHz. > Setting up local APIC 0x0 > CPU Index 0 - APIC 0 Unexpected Exception:6 @ 10:2ffb890d - Halting > Code: 0 eflags: 00010006 cr2: 00000000 > eax: 2ffb86ff ebx: 2ffc5e00 ecx: 00000000 edx: 000ba85f > edi: 00000000 esi: 00000000 ebp: 000f4240 esp: 2ffc8eb0 > > 0x2ffb88c8: c0 75 39 8b 4c 24 08 3b > 0x2ffb88d0: 4b 04 74 30 89 44 24 0c > 0x2ffb88d8: 83 ec 0c 6a 64 e8 9e ed > 0x2ffb88e0: ff ff 8b 44 24 1c 83 c4 > 0x2ffb88e8: 10 83 c0 64 39 c5 7f db > 0x2ffb88f0: 50 83 ce ff 57 68 dc 33 > 0x2ffb88f8: fc 2f 6a 03 e8 b7 0d 00 > 0x2ffb8900: 00 83 c4 10 8b 43 0c 85 > 0x2ffb8908: c0 74 02 ff d0 0f ae f0 > 0x2ffb8910: c7 03 01 00 00 00 47 eb > 0x2ffb8918: 9d 8b 44 24 2c 39 44 24 > 0x2ffb8920: 28 75 10 83 ec 0c 8d 44 > 0x2ffb8928: 24 38 50 e8 9a ed ff ff > 0x2ffb8930: 83 c4 10 8b 44 24 2c b9 > 0x2ffb8938: e8 03 00 00 2b 44 24 28 > 0x2ffb8940: 99 f7 f9 50 68 f4 33 fc > 0x2ffc8f2c: 0x2ffb29e6 > 0x2ffc8f28: 0x2ffc57c0 > 0x2ffc8f24: 0x2ffc9000 > 0x2ffc8f20: 0x2ffc4cc4 > 0x2ffc8f1c: 0x2ffc57c0 > 0x2ffc8f18: 0x2ffc8f38 > 0x2ffc8f14: 0x2ffc06c0 > 0x2ffc8f10: 0x2ffc4c80 > 0x2ffc8f0c: 0x2ffae2da > 0x2ffc8f08: 0x2ffc8fd8 > 0x2ffc8f04: 0x2ffc9000 > 0x2ffc8f00: 0x2ffc4cc4 > 0x2ffc8efc: 0x2ffc57c0 > 0x2ffc8ef8: 0x2ffc1b67 > 0x2ffc8ef4: 0x00000028 > 0x2ffc8ef0: 0x2ffcd320 > 0x2ffc8eec: 0x2ffb96ad > 0x2ffc8ee8: 0x2ffc8f38 > 0x2ffc8ee4: 0x2ffc178d > 0x2ffc8ee0: 0x000ba85f > 0x2ffc8edc: 0x000ba85f > 0x2ffc8ed8: 0x000ba85f > 0x2ffc8ed4: 0x00000004 > 0x2ffc8ed0: 0x2ffc5e00 > 0x2ffc8ecc: 0x00000000 > 0x2ffc8ec8: 0x00000000 > 0x2ffc8ec4: 0x00000001 > 0x2ffc8ec0: 0x2ffc1785 > 0x2ffc8ebc: 0x2ffc57c0 > 0x2ffc8eb8: 0x00000000 > 0x2ffc8eb4: 0x00000000 > 0x2ffc8eb0: 0x2ffc4cc4 <-esp > _______________________________________________ > coreboot mailing list -- [email protected] > To unsubscribe send an email to [email protected] >
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