Issue #457 has been updated by Arthur Heymans.
It is quite hard to relocate a binary (mrc.bin). This was done for the sandybridge using a hexeditor, but that is quite errorprone. Native init could use a different address but it is not as complete as the mrc.bin. For instance I think dram clocks will not run as high, some power reducing trainings are skipped and S3 resume is not implemented. ---------------------------------------- Bug #457: Haswell (t440p): CAR memory region should not conflict with CBFS_SIZE > 8mb https://ticket.coreboot.org/issues/457#change-1402 * Author: Thierry Laurion * Status: New * Priority: Normal * Target version: none * Start date: 2023-02-08 * Affected versions: 4.19, master ---------------------------------------- When neutering ME to pass freed space to IFD BIOS region (and having CBFS_SIZE match maximized IFD region), booting of the platform was reported to take an additional 20 seconds. A quick review at FOSDEM with a coreboot dev inspecting current Haswell code suggested that fixing DCACHE_RAM_BASE might fix the issue under src/northbridge/intel/haswell/Kconfig: 0xff7c0000 -> 0xfe7c0000 ----- Unfortunately, I have no access to a t440p to test the fix. It was also suggested that mrc.bin might need to be patched as well. But 4.19 is bringing native raminit, so that might not be an issue? Attached is the suggested change to be tested. ---Files-------------------------------- haswell_car_20230205233221.patch (369 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]
