Issue #658 has been updated by Angel Pons.
Hi Gabriel,
You may want to check the Super I/O datasheet to see what the registers do.
Each GPIO bank has a set of registers, with one bit per GPIO:
- I/O register: controls whether GPIOs are inputs or outputs
- Data register: shows/controls the logic level of GPIOs (read-only for inputs,
read-write for outputs)
- Inversion register: controls whether the value in the data register is
inverted ("data register value" = "actual GPIO logic level" XOR "inversion
register value")
- Status register: read to clear, set when a rising/falling edge is detected on
a GPIO
I'm not sure what 0xf3 controls, the bits being set to one appear as reserved
in my datasheet. But 0xf4/0xf5 are GPIO4 I/O and data registers respectively.
Looking at the boardview, pin 79 (GP46) is directly connected to the "ISOLATE"
pin of the Realtek NIC, which makes the NIC stop responding over PCIe as long
as the pin is asserted (not sure if it's active-high or active-low). To make
this work, you may want to try programming the Super I/O GPIOs in
bootblock/romstage. At the very least, program the registers for GPIO4.
You should also make sure that the BSEL code for the other two variants
(`early_init.c`) doesn't interfere with these Super I/O GPIO settings. On this
board, looks like Super I/O pins 82 and 81 (GP43 and GP44) are connected to
BSEL1 and BSEL2, respectively. BSEL0 does not seem to be connected to the Super
I/O. However, on the boardview I am looking at, it seems that some resistors
are missing so the Super I/O GPIOs do not actually connect to the BSELx pins at
all, so you may want to skip the code in `setup_sio_gpio()` (which actually
overwrites GPIO4 values).
About 0xe1/0xe2: 0xe2 is GPIO5 inversion register, and 0xe1 is GPIO5 data
register. 0xe0 is GPIO5 input/output register and its value is 0xff (all GPIOs
are inputs). So, writing 0x20 to 0xe2 will flip the value of the corresponding
bit in 0xe1. Given that, I would program 0xe2 the same as vendor firmware, even
if the value in 0xe1 is "more different" in this case (0xe1 is just showing the
values on GPIO5 pins, which are configured as inputs).
----------------------------------------
Bug #658: asus p5g41c-m-lx pcie discovery of realtek 10ec:8168
https://ticket.coreboot.org/issues/658#change-2361
* Author: Gabriel Turlea
* Status: New
* Priority: Normal
* Target version: none
* Start date: 2026-07-14
----------------------------------------
I have tried to port coreboot to asus-p5g41c-m-lx by using the existing
pg541t-m-lx variant. Everything works great except I cannot get the onboard lan
realtek 10ec:8168 to be detected by coreboot. The card shows up and works once
linux boots. Adding some register values in the overridetree.cb seems to
disable the card even in linux. Please let me know what supporting info I
should provide.
Thank you
---Files--------------------------------
p5g41c_m-lx_cbmem.log (53.5 KB)
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