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Hello,
I am trying to generate a Verilog Syntax Highlighting INI file. The Keywords
seem to work fine. However, I cannot seem to get the operators to show up.
Verilog has a number of operators including things like "&&" and "^^". I
created a string of operators, but it seems to be ignored. I simplified the
string down to a few basic arithmetic operators, but that too seems to be
ignored.
Is there a specification as to how the operators are input or delimited? I am
using version 1.013. Below is the operator line that I tried. But it does not
seem to work. Is there supposed to be a delimiter character between entries?
Operators=+-*/%>=<!&|~^?:'@
Thanks for your help.
--- Steve
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